Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
70
Datasheet
1.6.5
C0DRB3 - Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
206-207h
Default Value:
0000h
Access:
RW/L; RO;
Size: 16
bits
See C0DRB0
Bit Access Default
Value
RST/
PWR
Description
15:10 RO 000000b
Core
Reserved ():
9:0 RW/L 000h Core
Channel 0 DRAM Rank Boundary Address 3
(C0DRBA3):
This register defines the DRAM rank boundary
for rank3 of Channel 0 (64 MB granularity)
=(R3 + R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
(C0DRBA3):
This register defines the DRAM rank boundary
for rank3 of Channel 0 (64 MB granularity)
=(R3 + R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
1.6.6
C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
Address Offset:
208-209h
Default Value:
0000h
Access:
RW/L;
Size: 16
bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1:
208h-209h
Ch0 Rank2, 3:
20Ah-20Bh