Intel D425 AU80610006252AA User Manual

Datasheet 

 75 

B/D/F/Type: 0/0/0/MCHBAR 

Address Offset: 

258-25Ah 

Default Value: 

000000h 

Access: 

 RW; RO; 

Size: 24 

bits 

Channel 0 CYCTRK RD Registers. 

 

 

23:21 RO  000b Core 

Reserved ():  
Reserved.  

20:17 RW 

0h  Core 

Min ACT To READ Delayed (C0sd_cr_act_rd):  
This configuration register indicates the minimum 
allowed spacing (in DRAM clocks) between the ACT 
and READ commands to the same rank-bank. 
Corresponds to tRCD_rd at DDR Spec. 

16:12 RW  00000b Core 

Same Rank Write To READ Delayed 
(C0sd_cr_wrsr_rd):  
This configuration register indicates the minimum 
allowed spacing (in DRAM clocks) between the 
WRITE and READ commands to the same rank. 
Corresponds to tWTR at DDR Spec. 

11:8 RW  0000b Core 

Different Ranks Write To READ Delayed 
(C0sd_cr_wrdr_rd):  
This configuration register indicates the minimum 
allowed spacing (in DRAM clocks) between the 
WRITE and READ commands to different ranks. 
Corresponds to tWR_RD at DDR Spec. 

7:4 RW 0000b 

Core 

Same Rank Read To Read Delayed 
(C0sd_cr_rdsr_rd):  
This configuration register indicates the minimum 
allowed spacing (in DRAM clocks) between two READ 
commands to the same rank. 

3:0 RW 0000b 

Core 

Different Ranks Read To Read Delayed 
(C0sd_cr_rddr_rd):  
This configuration register indicates the minimum 
allowed spacing (in DRAM clocks) between two READ 
commands to different ranks. Corresponds to 
tRD_RD.