Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
99
1.8.1
EPESD - EP Element Self Description
B/D/F/Type: 0/0/0/PXPEPBAR
Address Offset:
44-47h
Default Value:
00000201h
Access:
RO; RWO;
Size: 32
bits
Provides information about the root complex element containing this Link Declaration
Capability.
Capability.
Bit Access Default
Value
RST/
PWR
Description
31:24 RO
00h Core
Port Number (PN)
This field specifies the port number associated
with this element with respect to the component
that contains this element. Value of 00 h
indicates to configuration software that this is
the default egress port.
This field specifies the port number associated
with this element with respect to the component
that contains this element. Value of 00 h
indicates to configuration software that this is
the default egress port.
23:16 RWO
00h Core
Component ID (CID)
Identifies the physical component that contains
this Root Complex Element. BIOS
Identifies the physical component that contains
this Root Complex Element. BIOS
Requirement: Must be initialized according to
guidelines in the PCI Express*
Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
guidelines in the PCI Express*
Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
15:8 RO 02h Core
Number of Link Entries (NLE):
Indicates the number of link entries following
the Element Self Description. This field reports 2
(one each for PEG and DMI).
Indicates the number of link entries following
the Element Self Description. This field reports 2
(one each for PEG and DMI).
7:4 RO 0h Core
Reserved ()
3:0 RO 1h Core
Element Type (ET)
Indicates the type of the Root Complex
Element. Value of 1 h represents a port to
system memory.
Indicates the type of the Root Complex
Element. Value of 1 h represents a port to
system memory.