Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
133
Processor Integrated I/O (IIO) Configuration Registers
3.4.6
System Control/Status Registers (Device 8, Function 2)
3.4.6.1
SYSMAP—System Error Event Map Register
This register maps the error severity detected by the IIO to one of the system events.
3.4.6.2
GENMCA—Generate MCA
This register is used to generate an Intel
®
Scalable Memory Interconnect (Intel SMI)
interrupt to the processor by firmware.
Register:
SYSMAP
Device:
8
Function:
2
Offset:
09Ch
Bit
Attr
Default
Description
31:7
RV
0
Reserved
6:4
RWS
010
Severity 1 Error Map
010 = Generate NMI
001 = Generate SMI
000 = No Inband Message
010 = Generate NMI
001 = Generate SMI
000 = No Inband Message
3
RV
0
Reserved
2:0
RWS
010
Severity 0 Error Map
010 = Generate NMI
001 = Generate SMI
000 = No Inband Message
010 = Generate NMI
001 = Generate SMI
000 = No Inband Message
Register:
GENMCA
Device:
8
Function:
2
Offset:
0C4h
Bit
Attr
Default
Description
31:1
RO
0
Reserved
0
RWS
0
Generate Intel SMI
When this bit is set and transition from 0 to 1, Integrated I/O dispatches a
When this bit is set and transition from 0 to 1, Integrated I/O dispatches a
MCA interrupt defined in the error MCA configuration register to the
processor. This bit is cleared by hardware when Integrated I/O has
dispatched MCA to the Intel QuickPath Interconnect link.
This bit should never be set since the processor does not support MCA
This bit should never be set since the processor does not support MCA