Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
135
Processor Integrated I/O (IIO) Configuration Registers
3.4.7.2
IIOSLPSTS_H—IIO Sleep Status High Register
3.4.7.3
PMUSTATE—Power Management State Register
Register:
IIOSLPSTS_H
Device:
8
Function:
3
Offset:
68h
Bit
Attr
Default
Description
31:12
RV
000h
Reserved
11:0
ROS
0h
SLPDUR_H: Sleep Duration High
This is the upper 12 bits of the IIOSLPSTS register field that indicates the
This is the upper 12 bits of the IIOSLPSTS register field that indicates the
number of clocks that the IIO has been put to sleep. The IIO will clear this
register on entry into sleep state and will increments it for every clock that the
IIO is asleep. This combined with IIOSLPSTS_L provides 2^44 clocks worth of
monitoring, or approximately 2^44*(1/133 MHz) = 131941s = 36.65 hours
(maximum).
Register:
PMUSTATE
Device:
8
Function:
3
Offset:
D8h
Bit
Attr
Default
Description
15
RV
00h
Reserved
14
ROS
0h
When set, this bit indicates that Intel
QuickPath Interconnect has transitioned to
L1.
13
ROS
0h
When set, this bit indicates that the IIO has sent the DMI translated Req->C7
message to the PCH.
12
ROS
0h
When set, this bit indicates that the IIO has sent the DMI translated Req>C6
message to the PCH.
11
ROS
0h
When set, this bit indicates that the IIO has sent the DMI translated Req->C3
message to the PCH.
10
ROS
0h
When set, this bit indicates that the PCH has acknowledged that it is in C7
9
ROS
0h
When set, this bit indicates that the PCH has acknowledged that it is in C6
8
ROS
0h
Indicates that the PCH has acknowledged that it is in C3
7:2
RV
00h
Reserved
1
ROS
0h
Set when the IIO (Integrated I/O) detects a Req C0 message on Intel
QuickPath
Interconnect
.
Can remain set until the next Req(C3/6/7) message
0
ROS
0h
Indicates that the PCH has acknowledged the ReqC0 message by returning the
InC0.Ack message on DMI