Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
134
Datasheet, Volume 2
3.4.6.3
SYRE—System Reset
This register controls IIO (Integrated I/O) Reset behavior. Any resets produced by a
write to this register must be delayed until the configuration write is completed on the
initiating interface (PCI Express, DMI, JTAG).
write to this register must be delayed until the configuration write is completed on the
initiating interface (PCI Express, DMI, JTAG).
There is no “SOFT RESET” bit in this register. That function is invoked through the DMI
interface. There are no Intel
interface. There are no Intel
QuickPath Interconnect PCI Express gear ratio definitions
in this register. The Intel
QuickPath Interconnect frequencies are specified in the FREQ
register. The PCI Express frequencies are automatically negotiated in-band.
3.4.7
Miscellaneous Registers (Dev:8, F:3)
3.4.7.1
IIOSLPSTS_L—IIO Sleep Status Low Register
Register:
SYRE
Device:
8
Function:
2
Offset:
0CCh
Bit
Attr
Default
Description
31:17
RV
0
Reserved
16
RV
0
Reserved
15
RV
0
Reserved
14
RV
0
Reserved
13:12
RV
0
Reserved
11
RW
0
RSTMSK
0 = The Integrated I/O will perform the appropriate internal handshakes on
0 = The Integrated I/O will perform the appropriate internal handshakes on
RSTIN# signal transitions to progress through the hard reset.
1 = Integrated I/O ignores RST_N, unaffected by the RST_N assertion.
10
RW
0
CPURESET
1 = IIO (Integrated I/O) asserts internal reset.
The IIO clears this bit when the CPURESET timer elapses.
The IIO clears this bit when the CPURESET timer elapses.
9:1
RV
0
Reserved
0
RV
0
Reserved
Register:
IIOSLPSTS_L
Device:
8
Function:
3
Offset:
64h
Bit
Attr
Default
Description
31:0
ROS
0h
SLPDUR_L: Sleep Duration Low
This is the lower 32 bits of the IIOSLPSTS register field that indicates the
This is the lower 32 bits of the IIOSLPSTS register field that indicates the
number of clocks that the Integrated I/O (IIO) has been put to sleep. The IIO
will clear this register on entry into sleep state and will increment it for every
clock that the IIO is asleep. This combined with IIOSLPSTS_H provides 2^44
clocks worth of monitoring, or approximately 2^44*(1/133 MHz) = 131941s =
36.65 hours (maximum).