Intel QX9775 EU80574XL088N Data Sheet

15

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the 

processor. As in previous processor generations, the processor core frequency is a 

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during 

manufacturing. The default setting is for the maximum speed of the processor. It is 

possible to override this setting using software (see the Intel

Architectures Software Developer’s Manual). This permits operation at lower 

frequencies than the processor’s tested frequency.

The processor core frequency is configured during reset by using values stored 

internally during manufacturing. The stored value sets the highest bus fraction at which 

the particular processor can operate. If lower speeds are desired, the appropriate ratio 

can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core 

frequencies lower than the maximum rated processor speed, refer to the Intel

Clock multiplying within the processor is provided by the internal phase locked loop 

(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread 

spectrum clocking. Processor DC specifications for the BCLK[1:0] inputs are provided in 

. These specifications must be met while also meeting signal integrity 

requirements as outlined in 

. The processor uses differential clocks. 

 contains processor core frequency to FSB multipliers and their corresponding 

core frequencies.

NOTES:
1.

Listed frequencies are not necessarily committed production frequencies.

2.

For valid processor core frequencies, see the Intel

3.

The lowest bus ratio supported by the processor is 1/6.

1/6

2.40 GHz

1, 2, 3

1/7

2.80 GHz

1, 2

1/7.5

3 GHz

1, 2

1/8

3.20 GHz

1, 2

1/8.5

3.40 GHz

1, 2

1/9

3.60 GHz

1, 2

1/9.5

3.80 GHz

1, 2

1/10

4 GHz

1, 2

1/10.5

4.20 GHz

1, 2

1/11

4.40 GHz

1, 2

1/11.5

4.60 GHz

1, 2

1/12

4.80 GHz

1, 2

1/12.5

5 GHz

1, 2

1/13

5.20 GHz

1, 2