Intel LF80550KF0604M Data Sheet
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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Introduction
1
Introduction
The Dual-Core Intel® Xeon® Processor 7100 Series, Processor Number 7150, 7140,
7130, 7120 and 7110 is a dual core product for multi-processor servers. The Dual-Core
Intel Xeon processor 7100 series is a 64-bit server processor utilizing two physical Intel
7130, 7120 and 7110 is a dual core product for multi-processor servers. The Dual-Core
Intel Xeon processor 7100 series is a 64-bit server processor utilizing two physical Intel
NetBurst® microarchitecture cores in one package. It maintains the tradition of
compatibility with IA-32 software and includes features found in the Intel® Xeon®
processor such as Hyper Pipelined Technology, a Rapid Execution Engine, and an
Execution Trace Cache. Hyper Pipelined Technology includes a multi-stage pipeline,
allowing the processor to reach much higher core frequencies. The 667 MTS (Mega
Transfer per Seconds) front side bus is a quad-pumped bus running off a 166 MHz
system clock making 5.3 GB per second data transfer rates possible. The 800 MTS front
side bus (FSB) is a quad-pumped bus running off a 200 MHz system clock making
6.4 GB per second data transfer rates possible. The Execution Trace Cache is a level 1
(L1) cache that stores decoded micro-operations, which removes the decoder from the
main execution path, thereby increasing performance. In addition, the Dual-Core Intel
Xeon processor 7100 series includes the Intel® Extended Memory 64 Technology,
providing additional address capability.
compatibility with IA-32 software and includes features found in the Intel® Xeon®
processor such as Hyper Pipelined Technology, a Rapid Execution Engine, and an
Execution Trace Cache. Hyper Pipelined Technology includes a multi-stage pipeline,
allowing the processor to reach much higher core frequencies. The 667 MTS (Mega
Transfer per Seconds) front side bus is a quad-pumped bus running off a 166 MHz
system clock making 5.3 GB per second data transfer rates possible. The 800 MTS front
side bus (FSB) is a quad-pumped bus running off a 200 MHz system clock making
6.4 GB per second data transfer rates possible. The Execution Trace Cache is a level 1
(L1) cache that stores decoded micro-operations, which removes the decoder from the
main execution path, thereby increasing performance. In addition, the Dual-Core Intel
Xeon processor 7100 series includes the Intel® Extended Memory 64 Technology,
providing additional address capability.
In addition, enhanced thermal and power management capabilities are implemented,
including Thermal Monitor, Thermal Monitor 2 (TM2), and Enhanced Intel SpeedStep®
technology. Thermal Monitor and Thermal Monitor 2 provide efficient and effective
cooling in high temperature situations. Enhanced Intel SpeedStep technology allows
trade-offs to be made between performance and power consumption. This may lower
average power consumption (in conjunction with OS support).
including Thermal Monitor, Thermal Monitor 2 (TM2), and Enhanced Intel SpeedStep®
technology. Thermal Monitor and Thermal Monitor 2 provide efficient and effective
cooling in high temperature situations. Enhanced Intel SpeedStep technology allows
trade-offs to be made between performance and power consumption. This may lower
average power consumption (in conjunction with OS support).
The Dual-Core Intel Xeon processor 7100 series supports Hyper-Threading Technology.
This feature allows a single, physical processor to function as two logical processors.
While some execution resources such as caches, execution units, and buses are shared,
each logical processor has its own architectural state with its own set of general-
purpose registers, control registers to provide increased system responsiveness in
multitasking environments, and headroom for next generation multi-threaded
applications. More information on Hyper-Threading Technology can be found at
This feature allows a single, physical processor to function as two logical processors.
While some execution resources such as caches, execution units, and buses are shared,
each logical processor has its own architectural state with its own set of general-
purpose registers, control registers to provide increased system responsiveness in
multitasking environments, and headroom for next generation multi-threaded
applications. More information on Hyper-Threading Technology can be found at
http://www.intel.com/technology/hyperthread
.
Support for Intel's Execute Disable Bit functionality has been added which can prevent
certain classes of malicious “buffer overflow” attacks when combined with a supporting
operating system. Execute Disable Bit allows the processor to classify areas in memory
by where application code can execute and where it cannot. When a malicious worm
attempts to insert code in the buffer, the processor disables code execution, preventing
damage or worm propagation.
certain classes of malicious “buffer overflow” attacks when combined with a supporting
operating system. Execute Disable Bit allows the processor to classify areas in memory
by where application code can execute and where it cannot. When a malicious worm
attempts to insert code in the buffer, the processor disables code execution, preventing
damage or worm propagation.
Other features within the Intel NetBurst microarchitecture include Advanced Dynamic
Execution, Advanced Transfer Cache, enhanced floating point and multi-media unit, and
Streaming SIMD Extensions 2 (SSE2). The Advanced Dynamic Execution improves
speculative execution and branch prediction internal to the processor. The Advanced
Transfer Cache is a 2 MB total on-die level 2 (L2) cache, organized as 1 MB dedicated
per core. The floating point and multi-media units include 128-bit wide registers and a
separate register for data movement. SSE2 instructions provide highly efficient double-
precision floating point, SIMD integer, and memory management operations. In
addition, Streaming SIMD Extensions 3 (SSE3) instructions have been added to further
extend the capabilities of Intel processor technology. Other processor enhancements
include core frequency improvements and microarchitectural improvements.
Execution, Advanced Transfer Cache, enhanced floating point and multi-media unit, and
Streaming SIMD Extensions 2 (SSE2). The Advanced Dynamic Execution improves
speculative execution and branch prediction internal to the processor. The Advanced
Transfer Cache is a 2 MB total on-die level 2 (L2) cache, organized as 1 MB dedicated
per core. The floating point and multi-media units include 128-bit wide registers and a
separate register for data movement. SSE2 instructions provide highly efficient double-
precision floating point, SIMD integer, and memory management operations. In
addition, Streaming SIMD Extensions 3 (SSE3) instructions have been added to further
extend the capabilities of Intel processor technology. Other processor enhancements
include core frequency improvements and microarchitectural improvements.