Intel LF80550KF0604M Data Sheet
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
13
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating that a signal
is in the asserted state when driven to a low level. For example, when RESET# is low
(i.e. when RESET# is asserted), a reset has been requested. Conversely, when NMI is
high (i.e. when NMI is asserted), a nonmaskable interrupt request has occurred. In the
case of signals where the name does not imply an active state but describes part of a
binary sequence (such as address or data), the ‘#’ symbol implies that the signal is
inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also
refers to a hex ‘A’ (H= High logic level, L= Low logic level).
is in the asserted state when driven to a low level. For example, when RESET# is low
(i.e. when RESET# is asserted), a reset has been requested. Conversely, when NMI is
high (i.e. when NMI is asserted), a nonmaskable interrupt request has occurred. In the
case of signals where the name does not imply an active state but describes part of a
binary sequence (such as address or data), the ‘#’ symbol implies that the signal is
inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also
refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front side bus” refers to the interface between the processor, system core logic (i.e.
the chipset components), and other bus agents. The front side bus supports
multiprocessing and cache coherency. For this document, “front side bus” is used as the
generic term for the “Dual-Core Intel Xeon processor 7100 series system bus”.
the chipset components), and other bus agents. The front side bus supports
multiprocessing and cache coherency. For this document, “front side bus” is used as the
generic term for the “Dual-Core Intel Xeon processor 7100 series system bus”.
Commonly used terms are explained here for clarification:
• Enhanced Intel SpeedStep Technology — Enhanced Intel SpeedStep
Technology is the next generation implementation of the Geyserville technology
which extends power management capabilities of servers.
which extends power management capabilities of servers.
• FC-mPGA6 — The Dual-Core Intel Xeon processor 7100 series is available in a
Flip-Chip Micro Pin Grid Array 6 package, consisting of a processor core mounted
on a pinned substrate with an integrated heat spreader (IHS). This packaging
technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.
on a pinned substrate with an integrated heat spreader (IHS). This packaging
technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.
• Front Side Bus (FSB) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Functional Operation — Refers to the normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical,
and thermal, are satisfied.
and thermal, are satisfied.
• Integrated Heat Spreader (IHS) — A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
interface with the processor at the IHS surface.
• mPGA604 — The Dual-Core Intel Xeon processor 7100 series processor mates
with the system board through this surface mount, 604-pin, zero insertion force
(ZIF) socket.
(ZIF) socket.
• OEM — Original Equipment Manufacturer.
• Processor core — The processor’s execution engine. All AC timing and signal
• Processor core — The processor’s execution engine. All AC timing and signal
integrity specifications are to the pads of the processor core.
• Processor Information ROM (PIROM) — A memory device located on the
processor and accessible via the System Management Bus (SMBus) which contains
information regarding the processor’s features. This device is shared with the
Scratch EEPROM, is programmed during manufacturing, and is write-protected.
information regarding the processor’s features. This device is shared with the
Scratch EEPROM, is programmed during manufacturing, and is write-protected.
• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)
— A memory device located on the processor and addressable via the SMBus which
can be used by the OEM to store information useful for system management.
can be used by the OEM to store information useful for system management.
• SMBus — System Management Bus. A two-wire interface through which simple
system and power management related devices can communicate with the rest of
the system. It is based on the principals of the operation of the I
the system. It is based on the principals of the operation of the I
2
C* two-wire serial
bus from Phillips Semiconductor.