Intel LF80550KF0604M Data Sheet
Electrical Specifications
18
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Note:
Some AGTL+ signals do not include on-die termination (R
TT
) and must be terminated
on the motherboard. See
for details regarding these signals.
2.1.1
Front Side Bus Clock and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core
frequency of the processor. The Dual-Core Intel® Xeon® Processor 7100 Series
processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus
ratio multiplier will be set at its default ratio during manufacturing. The default setting
generates the maximum speed for the processor. It is possible to override this setting
using software. Refer to the Cedar Mill Processor Family BIOS Writer’s Guide for details.
This will permit operation at a speed lower than the processor’s tested frequency.
frequency of the processor. The Dual-Core Intel® Xeon® Processor 7100 Series
processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus
ratio multiplier will be set at its default ratio during manufacturing. The default setting
generates the maximum speed for the processor. It is possible to override this setting
using software. Refer to the Cedar Mill Processor Family BIOS Writer’s Guide for details.
This will permit operation at a speed lower than the processor’s tested frequency.
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored values set the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate bus
ratio multiplier can be configured by driving the A[21:16]# pins at reset. For details of
operation at core frequencies lower than the maximum rated processor speed, refer to
the Cedar Mill Processor Family BIOS Writer’s Guide.
internally during manufacturing. The stored values set the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate bus
ratio multiplier can be configured by driving the A[21:16]# pins at reset. For details of
operation at core frequencies lower than the maximum rated processor speed, refer to
the Cedar Mill Processor Family BIOS Writer’s Guide.
The bus ratio multipliers supported are shown in
and
. Other
combinations will not be validated or supported by Intel. For a given processor, only the
ratios which result in a core frequency equal to or less than the frequency marked on
the processor are supported.
ratios which result in a core frequency equal to or less than the frequency marked on
the processor are supported.
Figure 2-1. On-Die Front Side Bus Termination
End Agent
Signal
V
TT
Middle Agent
R
TT
Signal
R
L
R
TT
- On-die termination resistors for AGTL+ signals
R
L
- Additional on-die resistance implemented for proper noise margin and
signal integrity (wired-OR signals only)
Table 2-1.
166 MHz Core Frequency to Front Side Bus Multiplier Configuration
(Sheet 1 of 2)
Core Frequency
to Front Side Bus
Multiplier
Core Frequency
(166 MHz)
A21#
A20#
A19#
A18#
A17#
A16#
1/15
2.5 GHz
H
H
L
L
L
L
1/18
3 GHz
H
L
H
H
L
H