Intel LF80550KF0604M Data Sheet
Electrical Specifications
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
19
Notes:
1.
Individual processors operate only at or below the frequency marked on the package.
2.
Listed frequencies are not necessarily committed production frequencies.
3.
For valid core frequencies of the processor, refer to the Dual-Core Intel® Xeon® Processor 7100 Series
Specification Update.
4.
As described in
, “H” refers to a high logic level (i.e. signal asserted) and “L” refers to a low logic
level (i.e. signal deasserted).
Notes:
1.
Individual processors operate only at or below the frequency marked on the package.
2.
Listed frequencies are not necessarily committed production frequencies.
3.
For valid core frequencies of the processor, refer to the Dual-Core Intel® Xeon® Processor 7100 Series
Specification Update.
4.
As described in
, “H” refers to a high logic level (i.e. signal asserted) and “L” refers to a low logic
level (i.e. signal deasserted).
The Dual-Core Intel Xeon processor 7100 series uses a differential clocking
implementation. For more information on the Dual-Core Intel Xeon processor 7100
series clocking, refer to the appropriate clock driver design guidelines.
implementation. For more information on the Dual-Core Intel Xeon processor 7100
series clocking, refer to the appropriate clock driver design guidelines.
2.1.2
Front Side Bus Clock Select (BSEL[1:0])
The BSEL[1:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]).
(BCLK[1:0]).
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All processors must operate at the same
front side bus frequency.
the processor, chipset, and clock synthesizer. All processors must operate at the same
front side bus frequency.
The Dual-Core Intel Xeon processor 7100 series operates at a 667 MTS or 800 MTS
front side bus frequency (selected by a 166 MHz or 200 MHz BCLK[1:0] frequency).
Individual processors operate at the front side bus frequency specified by BSEL[1:0].
front side bus frequency (selected by a 166 MHz or 200 MHz BCLK[1:0] frequency).
Individual processors operate at the front side bus frequency specified by BSEL[1:0].
For more information about these pins, refer to
and the appropriate
platform design guide.
1/19
3.16 GHz
H
L
H
H
L
L
1/20
3.33 GHz
H
L
H
L
H
H
1/21
3.50 GHz
H
L
H
L
H
L
Table 2-1.
166 MHz Core Frequency to Front Side Bus Multiplier Configuration
(Sheet 2 of 2)
Core Frequency
to Front Side Bus
Multiplier
Core Frequency
(166 MHz)
A21#
A20#
A19#
A18#
A17#
A16#
Table 2-2.
200 MHz Core Frequency to Front Side Bus Multiplier Configuration
Core Frequency
to Front Side Bus
Multiplier
Core Frequency
(200MHz)
A21#
A20#
A19#
A18#
A17#
A16#
1/13
2.6 GHz
H
H
L
L
H
L
1/15
3 GHz
H
H
L
L
L
L
1/16
3.20 GHz
H
L
H
H
H
H
1/17
3.40 GHz
H
L
H
H
H
L