Intel LF80550KF0604M Data Sheet
Features
84
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
the bus before allowing the processor to be transitioned into one of the lower processor
power states. Refer to the applicable chipset specification and the Cedar Mill Processor
Family BIOS Writer’s Guide for more information.
power states. Refer to the applicable chipset specification and the Cedar Mill Processor
Family BIOS Writer’s Guide for more information.
7.2.1
Normal State
This is the normal operating state for the processor.
7.2.2
HALT or Enhanced Power Down State
The Enhanced HALT power down state is configured and enabled via the BIOS. Refer to
the Cedar Mill Processor Family BIOS Writer’s Guide for Enhanced HALT state
configuration information. If the Enhanced HALT state is not enabled, the default power
down state entered will be HALT. Refer to the section below for details on HALT and
Enhanced HALT states.
the Cedar Mill Processor Family BIOS Writer’s Guide for Enhanced HALT state
configuration information. If the Enhanced HALT state is not enabled, the default power
down state entered will be HALT. Refer to the section below for details on HALT and
Enhanced HALT states.
7.2.2.1
HALT Power Down State
HALT is a low power state entered when all logical processors have executed the HALT
or MWAIT instruction. When one of the logical processors executes the HALT or MWAIT
instruction, that logical processor is halted; however, the other processor continues
normal operation. The processor transitions to the Normal state upon the occurrence of
SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front
side bus. RESET# causes the processor to immediately initialize itself.
or MWAIT instruction. When one of the logical processors executes the HALT or MWAIT
instruction, that logical processor is halted; however, the other processor continues
normal operation. The processor transitions to the Normal state upon the occurrence of
SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front
side bus. RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the IA-32 Intel
Normal Mode or the HALT Power Down state. See the IA-32 Intel
®
Architecture Software
Developer's Manual, Volume III: System Programming Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor returns
execution to the HALT state.
state. When the system deasserts the STPCLK# interrupt, the processor returns
execution to the HALT state.
While in HALT Power Down state, the processor processes bus snoops and interrupts.
7.2.2.2
Enhanced HALT Power Down State
Enhanced HALT state is a low power state entered when all logical processors have
executed the HALT or MWAIT instructions and Enhanced HALT state has been enabled
via the BIOS. When one of the logical processors executes the HALT instruction, that
logical processor is halted; however, the other processor continues normal operation.
The Enhanced HALT state is generally a lower power state than the Stop Grant state.
executed the HALT or MWAIT instructions and Enhanced HALT state has been enabled
via the BIOS. When one of the logical processors executes the HALT instruction, that
logical processor is halted; however, the other processor continues normal operation.
The Enhanced HALT state is generally a lower power state than the Stop Grant state.
The processor automatically transitions to a lower core frequency and voltage operating
point before entering the Enhanced HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
point before entering the Enhanced HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
While in the Enhanced HALT state, the processor processes bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the
processor exits the Enhanced HALT state, it first transitions the VID to the original
value and then changes the bus ratio back to the original value.
processor exits the Enhanced HALT state, it first transitions the VID to the original
value and then changes the bus ratio back to the original value.