Intel LF80550KF0604M Data Sheet
Features
86
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
While in Stop-Grant state, the processor processes snoops on the front side bus and
latches interrupts delivered on the front side bus.
latches interrupts delivered on the front side bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is
asserted if there is any pending interrupt latched within the processor. Pending
interrupts that are blocked by the EFLAGS.IF bit being clear still cause assertion of
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to
the Normal state.
asserted if there is any pending interrupt latched within the processor. Pending
interrupts that are blocked by the EFLAGS.IF bit being clear still cause assertion of
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to
the Normal state.
7.2.4
Enhanced HALT Snoop State or HALT Snoop State,
Stop Grant Snoop State
The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state.
If Enhanced HALT state is not enabled in the BIOS, the default Snoop state entered will
be the HALT Snoop state. Refer to the sections below for details on HALT Snoop state,
Grant Snoop state and Enhanced HALT Snoop state.
If Enhanced HALT state is not enabled in the BIOS, the default Snoop state entered will
be the HALT Snoop state. Refer to the sections below for details on HALT Snoop state,
Grant Snoop state and Enhanced HALT Snoop state.
7.2.4.1
HALT Snoop State, Stop Grant Snoop State
The processor responds to snoop or interrupt transactions on the front side bus while in
Stop-Grant state or in HALT Power Down state. During a snoop or interrupt transaction,
the processor enters the HALT/Grant Snoop state. The processor stays in this state
until the snoop on the front side bus has been serviced (whether by the processor or
another agent on the front side bus) or the interrupt has been latched. After the snoop
is serviced or the interrupt is latched, the processor will return to the Stop-Grant state
or HALT Power Down state, as appropriate.
Stop-Grant state or in HALT Power Down state. During a snoop or interrupt transaction,
the processor enters the HALT/Grant Snoop state. The processor stays in this state
until the snoop on the front side bus has been serviced (whether by the processor or
another agent on the front side bus) or the interrupt has been latched. After the snoop
is serviced or the interrupt is latched, the processor will return to the Stop-Grant state
or HALT Power Down state, as appropriate.
7.2.4.2
Enhanced HALT Snoop State
The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT
state is enabled via the BIOS. The processor remains in the lower bus ratio and VID
operating point of the Enhanced HALT state.
state is enabled via the BIOS. The processor remains in the lower bus ratio and VID
operating point of the Enhanced HALT state.
While in the Enhanced HALT Snoop state, snoops and interrupt transactions are
handled the same way as in the HALT Snoop state. After the snoop is serviced or the
interrupt is latched, the processor returns to the Enhanced HALT state.
handled the same way as in the HALT Snoop state. After the snoop is serviced or the
interrupt is latched, the processor returns to the Enhanced HALT state.
7.3
Enhanced Intel SpeedStep® Technology
Enhanced Intel SpeedStep Technology enables the processor to switch between
frequency and voltage points, which may result in platform power savings. In order to
support this technology, the system must support dynamic VID transitions. Switching
between voltage/frequency states is software controlled. For more configuration details
also refer to the Cedar Mill Processor Family BIOS Writer's Guide.
frequency and voltage points, which may result in platform power savings. In order to
support this technology, the system must support dynamic VID transitions. Switching
between voltage/frequency states is software controlled. For more configuration details
also refer to the Cedar Mill Processor Family BIOS Writer's Guide.
Note:
Not all processors are capable of supporting Enhanced Intel SpeedStep Technology.
More details on which processor frequencies will support this feature will be provided in
future releases of the NDA Specification Update.
Enhanced Intel SpeedStep Technology is a technology that creates processor
performance states (P-states). P-states are power consumption and capability states
within the Normal state. Enhanced Intel SpeedStep technology enables real-time
dynamic switching between frequency and voltage points. It alters the performance of
the processor by changing the bus to core frequency ratio and voltage. This allows the
processor to run at different core frequencies and voltages to best serve the
performance states (P-states). P-states are power consumption and capability states
within the Normal state. Enhanced Intel SpeedStep technology enables real-time
dynamic switching between frequency and voltage points. It alters the performance of
the processor by changing the bus to core frequency ratio and voltage. This allows the
processor to run at different core frequencies and voltages to best serve the