Intel 530 LF80537NE0301M Data Sheet

Datasheet

11

The processor supports the C1/AutoHALT, C1/MWAIT, C2, C3 and some support the C4 

core low-power states, along with their corresponding package-level states for power 

management. See Chapter 3 to see if C4 is supported. These package states include 

Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep Sleep. The processor’s central 

power management logic enters a package low-power state by initiating a P_LVLx 

(P_LVL2, P_LVL3, P_LVL4) I/O read to the (G)MCH. 

 shows the package-level 

low-power states and 

 shows the core low-power states. Refer to 

 for a 

mapping of core low-power states to package low-power states.

The processor implements two software interfaces for requesting low-power states: 

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK 

register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are 

converted to equivalent MWAIT C-state requests inside the processor and do not 

directly result in I/O reads on the processor FSB. The monitor address does not need to 

be setup before using the P_LVLx I/O read interface. The sub-state hints used for each 

P_LVLx read can be configured through the IA32_MISC_ENABLES Model Specific 

Register (MSR).

If the processor encounters a chipset break event while STPCLK# is asserted, it asserts 

the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to 

system logic that the processor should return to the Normal state.

NOTE: AutoHALT or MWAIT/C1

C0

Normal

C1

(1)

Normal

C2

Stop Grant

C3

Deep Sleep

C4

Deeper Sleep

STPCLK# asserted

Snoop

serviced

Snoop

occurs

SLP# asserted

SLP# deasserted

DPSLP# asserted

DPSLP# deasserted

DPRSTP# deasserted

DPRSTP# asserted

STPCLK# deasserted

† — Deeper Sleep includes the Deeper Sleep state and Deep C4 sub-state