Intel 530 LF80537NE0301M Data Sheet
Product codes
LF80537NE0301M
Low Power Features
12
Datasheet
2.1.1
Core Low-Power States
2.1.1.1
C0 State
This is the normal operating state of the processor.
2.1.1.2
C1/AutoHALT Powerdown State
C1/AutoHALT is a low-power state entered when the processor core executes the HALT
instruction. The processor core transitions to the C0 state upon the occurrence of
SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# causes the
processor to immediately initialize itself.
A System Management Interrupt (SMI) A System Management Interrupt (SMI) handler
returns execution to either Normal state or the C1/AutoHALT Powerdown state. See the
Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A/3B:
System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the C1/AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
returns execution to the HALT state.
The processor in C1/AutoHALT powerdown state process only the bus snoops. The
processor enters a snoopable sub-state (not shown in
) to process the snoop
and then return to the C1/AutoHALT Powerdown state.
Figure 2.
Core Low-Power States
C2
†
C0
Stop
Grant
Core state
break
P_LVL2 or
MWAIT(C2)
C3
†
Core
state
break
P_LVL3 or
MWAIT(C3)
C1/MWAIT
Core state
break
MWAIT(C1)
C1/Auto
Halt
Halt break
HLT instruction
C4
† ‡
Core State
break
P_LVL4
MWAIT(C4)
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
e state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
Core C4 state supports the package level Deep C4 sub-state.