Intel 530 LF80537NE0301M Data Sheet

Datasheet

13

C1/MWAIT is a low-power state entered when the processor core executes the MWAIT 

instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT 

state except that there is an additional event that can cause the processor core to 

return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel® 

for more information.

The core of the processor can enter the C2 state by initiating a P_LVL2 I/O read to the 

P_BLK or an MWAIT(C2) instruction, but the processor does not issue a Stop Grant 

Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

The processor in C2 state processes only the bus snoops. The processor enters a 

snoopable sub-state (not shown in 

) to process the snoop and then return to 

the C2 state.

Core C3 state is a very low-power state the processor core can enter while maintaining 

context. The core of the processor can enter the C3 state by initiating a P_LVL3 I/O 

read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the 

processor core flushes the contents of its L1 cache into the processor’s L2 cache. 

Except for the caches, the processor core maintains all its architectural state in the C3 

state. The Monitor remains armed if it is configured. All of the clocks in the processor 

core are stopped in the C3 state. 

Because the core’s caches are flushed, the processor keeps the core in the C3 state 

when the processor detects a snoop on the FSB. The processor core transitions to the 

C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), 

or FSB interrupt message. RESET# causes the processor core to immediately initialize 

itself.

Individual cores of the dual-core processor that have C4 can enter the C4 state by 

initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor 

core behavior in the C4 state is nearly identical to the behavior in the C3 state. The 

only difference is that if both processor cores are in C4, the central power management 

logic will request that the entire processor enter the Deeper Sleep package low-power 

)

Package level low-power states are applicable to the processor. 

This is the normal operating state for the processor. The processor enters the Normal 

state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.

When the STPCLK# pin is asserted the core of the processor enters the Stop-Grant 

state within 20 bus clocks after the response phase of the processor-issued Stop Grant 

Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core returns 

to the previous core low-power state.