Intel 41210 User Manual
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
35
PCI-X Interface
3.3.4
Split Transactions
•
•
Unexpected Split Completions
The 41210 asserts DEVSEL# and discards the data when the Requester ID matches the bridge
but the tag does not match that of any outstanding requests (0 or 1) from this device.
but the tag does not match that of any outstanding requests (0 or 1) from this device.
•
Split Completion Messages
The 41210 can generate error messages only for cycles that cross the bridge that master- or
target-abort. At this point, Dword cycles cross the bridge that requires completion (in other
words, I/O cycles). Therefore, the 41210 can generate only a “PCI-X Bridge Error”
completion message for the memory read commands, as indicated in
target-abort. At this point, Dword cycles cross the bridge that requires completion (in other
words, I/O cycles). Therefore, the 41210 can generate only a “PCI-X Bridge Error”
completion message for the memory read commands, as indicated in
.
3.4
Arbitration
The 41210 supports a high-performance internal PCI arbiter that supports up to five external masters on
each PCI segment. The request inputs into the internal arbiter include five external request inputs and
one internal request input. All request inputs to the internal arbiter are split into two groups: a high
priority group and a low priority group. Any master, including the internal master,
each PCI segment. The request inputs into the internal arbiter include five external request inputs and
one internal request input. All request inputs to the internal arbiter are split into two groups: a high
priority group and a low priority group. Any master, including the internal master,
can be programmed
to be in either of the two groups. The request inputs into the arbiter can be in one single group. Within a
group, priority is round-robin. The entire low-priority group represents one slot in the high-priority
group. The 41210 provides a 16-bit arbiter control register to control two aspects of the internal arbiter
behavior:
group, priority is round-robin. The entire low-priority group represents one slot in the high-priority
group. The 41210 provides a 16-bit arbiter control register to control two aspects of the internal arbiter
behavior:
•
Priority group for a master (in other words, whether a master is in the low-priority group or the
high-priority group)
high-priority group)
•
Bus parking on last PCI agent or the bridge
Table 17.
Intel
®
41210 Serial to Parallel PCI Bridge Implementation of Completer Attribute
Fields
Attribute
Function
Byte Count Modified (BCM)
The 41210 does not set this bit.
Split Completion Error (SCE)
The 41210 sets this bit only in the following
circumstances:
circumstances:
•
when a memory read command from PCI-X
master is target aborted on PCI Express*
master is target aborted on PCI Express*
•
when the 41210 does a queue discard operation
of upstream queues
of upstream queues
Split Completion Message (SCM)
This bit shadows the SCE bit.
Table 18.
Split Completion Abort Registers
Index
Message
00h
Master-Abort: The 41210 encountered a Master-Abort on the destination bus.
01h
Target-Abort: The 41210 encountered a Master-Abort on the destination bus