Intel architecture ia-32 User Manual
Vol. 3A 14-3
MACHINE-CHECK ARCHITECTURE
Where:
•
Count field, bits 0 through 7 — Indicates the number of hardware unit error-reporting
banks available in a particular processor implementation.
banks available in a particular processor implementation.
•
MCG_CTL_P (control MSR present) flag, bit 8 — Indicates that the processor
implements the IA32_MCG_CTL MSR when set; this register is absent when clear.
implements the IA32_MCG_CTL MSR when set; this register is absent when clear.
•
MCG_EXT_P (extended MSRs present) flag, bit 9 — Indicates that the processor
implements the extended machine-check state registers found starting at MSR address
180H; these registers are absent when clear.
implements the extended machine-check state registers found starting at MSR address
180H; these registers are absent when clear.
•
MCG_EXT_CNT, bits 16 through 23 — Indicates the number of extended machine-
check state registers present. This field is meaningful only when the MCG_EXT_P flag is
set.
check state registers present. This field is meaningful only when the MCG_EXT_P flag is
set.
Bits 15-10 and 63-24 are reserved. The effect of writing to the IA32_MCG_CAP register is
undefined.
undefined.
14.3.1.2
MCG_CAP MSR (P6 Family Processors)
The MCG_CAP MSR is a read-only register that provides information about the machine-check
architecture implementation in P6 family processors (see Figure 14-3).
architecture implementation in P6 family processors (see Figure 14-3).
Figure 14-2. IA32_MCG_CAP Register
Figure 14-3. MCG_CAP Register
MCG_CTL_P
63
0
Reserved
7
Count
8
9
10
15
16
23
24
MCG_EXT_P
MCG_EXT_CNT
Reserved
Count—Number of reporting banks
MCG_CTL_P—MCG_CTL register present
63
0
Reserved
7
Count
8
9