Intel architecture ia-32 User Manual
Vol. 3A 14-5
MACHINE-CHECK ARCHITECTURE
14.3.1.4
IA32_MCG_CTL MSR
The IA32_MCG_CTL MSR (called the MCG_CTL MSR in P6 family processors) is present if
the capability flag MCG_CTL_P is set in the IA32_MCG_CAP MSR (or the MCG_CAP MSR).
the capability flag MCG_CTL_P is set in the IA32_MCG_CAP MSR (or the MCG_CAP MSR).
IA32_MCG_CTL (or MCG_CTL) controls the reporting of machine-check exceptions. If
present, writing 1s to this register enables machine-check features and writing all 0s disables
machine-check features. All other values are undefined and/or implementation specific.
present, writing 1s to this register enables machine-check features and writing all 0s disables
machine-check features. All other values are undefined and/or implementation specific.
14.3.2
Error-Reporting Register Banks
Each error-reporting register bank can contain the IA32_MCi_CTL, IA32_MCi_STATUS,
IA32_MCi_ADDR, and IA32_MCi_MISC MSRs (called MCi_CTL, MCi_STATUS,
MCi_ADDR, and MCi_MISC in P6 family processors). The Pentium 4 and Intel Xeon proces-
sors provide four or five banks; the P6 family processors provide five banks. The first error-
reporting register (IA32_MC0_CTL) always starts at address 400H.
IA32_MCi_ADDR, and IA32_MCi_MISC MSRs (called MCi_CTL, MCi_STATUS,
MCi_ADDR, and MCi_MISC in P6 family processors). The Pentium 4 and Intel Xeon proces-
sors provide four or five banks; the P6 family processors provide five banks. The first error-
reporting register (IA32_MC0_CTL) always starts at address 400H.
See Appendix B, “Model-Specific Registers (MSRs),” for addresses of the error-reporting regis-
ters in the Pentium 4 and Intel Xeon processors; and for addresses of the error-reporting registers
P6 family processors.
ters in the Pentium 4 and Intel Xeon processors; and for addresses of the error-reporting registers
P6 family processors.
14.3.2.1
IA32_MCi_CTL MSRs
The IA32_MCi_CTL MSR (called MCi_CTL in P6 family processors) controls error reporting
for errors produced by a particular hardware unit (or group of hardware units). Each of the 64
flags (EEj) represents a potential error. Setting an EEj flag enables reporting of the associated
error and clearing it disables reporting of the error. The processor does not write changes to bits
that are not implemented. Figure 14-5 shows the bit fields of IA32_MCi_CTL.
for errors produced by a particular hardware unit (or group of hardware units). Each of the 64
flags (EEj) represents a potential error. Setting an EEj flag enables reporting of the associated
error and clearing it disables reporting of the error. The processor does not write changes to bits
that are not implemented. Figure 14-5 shows the bit fields of IA32_MCi_CTL.
NOTE
For P6 family processors only: the operating system or executive software
must not modify the contents of the MC0_CTL MSR. This MSR is internally
aliased to the EBL_CR_POWERON MSR and controls platform-specific
error handling features. System specific firmware (the BIOS) is responsible
for the appropriate initialization of the MC0_CTL MSR. P6 family
processors only allow the writing of all 1s or all 0s to the MCi_CTL MSR.
must not modify the contents of the MC0_CTL MSR. This MSR is internally
aliased to the EBL_CR_POWERON MSR and controls platform-specific
error handling features. System specific firmware (the BIOS) is responsible
for the appropriate initialization of the MC0_CTL MSR. P6 family
processors only allow the writing of all 1s or all 0s to the MCi_CTL MSR.
Figure 14-5. IA32_MCi_CTL Register
EEj—Error reporting enable flag
63
0
1
2
3
E
E
E
0
1
1
E
E
E
0
2
2
E
E
E
0
0
0
E
E
E
6
1
1
E
E
E
6
2
2
E
E
E
6
3
3
62 61
. . . . .
(where j is 00 through 63)