Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Datasheet, Volume 1
49
Electrical Specifications
7
Electrical Specifications
7.1
Processor Signaling
The processor includes 2011 lands that use various signaling technologies. Signals are
grouped by electrical characteristics and buffer type into various signal groups. These
include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*, DMI2,
Platform Environmental Control Interface (PECI), System Reference Clock, SMBus,
JTAG and Test Access Port (TAP), SVID Interface, Processor Asynchronous Sideband,
Miscellaneous, and Power/Other signals. Refer to
grouped by electrical characteristics and buffer type into various signal groups. These
include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*, DMI2,
Platform Environmental Control Interface (PECI), System Reference Clock, SMBus,
JTAG and Test Access Port (TAP), SVID Interface, Processor Asynchronous Sideband,
Miscellaneous, and Power/Other signals. Refer to
Table 7-5
for details.
Intel strongly recommends performing analog simulations of all interfaces. Refer to
Section 1.7, “Related Documents”
for signal integrity model availability.
7.1.1
System Memory Interface Signal Groups
The system memory interface uses DDR3 technology that consists of numerous signal
groups. These groups include – Reference Clocks, Command Signals, Control Signals,
and Data Signals. Each group consists of numerous signals that may use various
signaling technologies. Refer to
groups. These groups include – Reference Clocks, Command Signals, Control Signals,
and Data Signals. Each group consists of numerous signals that may use various
signaling technologies. Refer to
Table 7-5
for further details. Throughout this chapter,
the system memory interface maybe referred to as DDR3.
7.1.2
PCI Express* Signals
The PCI Express Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI
Express miscellaneous signals. Refer to
Express miscellaneous signals. Refer to
Table 7-5
for further details.
Note:
The processor is capable of up to 8.0 GT/s speeds.
7.1.3
DMI2/PCI Express* Signals
The Direct Media Interface (DMI2) Gen 2 sends and receives packets and/or commands
to the PCH. The DMI2 is an extension of the standard PCI Express Specification. The
DMI2/PCI Express Signals consist of DMI2 receive and transmit input/output signals
and a control signal. Refer to
to the PCH. The DMI2 is an extension of the standard PCI Express Specification. The
DMI2/PCI Express Signals consist of DMI2 receive and transmit input/output signals
and a control signal. Refer to
Table 7-5
for further details.
7.1.4
Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external system management logic and
thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS)
that reports a relative die temperature as an offset from Thermal Control Circuit (TCC)
activation temperature. Temperature sensors located throughout the die are
implemented as analog-to-digital converters calibrated at the factory. PECI provides an
interface for external devices to read processor temperature, perform processor
manageability functions, and manage processor interface tuning and diagnostics. Refer
to
Intel processors and chipset components to external system management logic and
thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS)
that reports a relative die temperature as an offset from Thermal Control Circuit (TCC)
activation temperature. Temperature sensors located throughout the die are
implemented as analog-to-digital converters calibrated at the factory. PECI provides an
interface for external devices to read processor temperature, perform processor
manageability functions, and manage processor interface tuning and diagnostics. Refer
to
Section 2.4, “Platform Environment Control Interface (PECI)”
for processor specific
implementation details for PECI. Refer to the processor Thermal Mechanical
Specification and Design Guide (see
Specification and Design Guide (see
Section 1.7, “Related Documents”
) for additional
details regarding PECI and for a list of supported PECI commands.