Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Datasheet, Volume 1
51
Electrical Specifications
7.1.6
JTAG and Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the JTAG and Test Access
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
7.1.7
Processor Sideband Signals
The processor includes asynchronous sideband signals that provide asynchronous
input, output or I/O signals between the processor and the platform or Platform
Controller Hub. Details can be found in
input, output or I/O signals between the processor and the platform or Platform
Controller Hub. Details can be found in
Table 7-5
.
All processor Asynchronous Sideband signals are required to be asserted/deasserted
for a defined number of BCLKs in order for the processor to recognize the proper signal
state. These are outlined in
for a defined number of BCLKs in order for the processor to recognize the proper signal
state. These are outlined in
Table 7-18
(DC specifications).
7.1.8
Power, Ground and Sense Signals
Processors also include various other signals including power/ground and sense points.
Details can be found in
Details can be found in
Table 7-5
.
7.1.8.1
Power and Ground Lands
All VCC, VCCPLL, VSA, VCCD, VTTA, and VTTD lands must be connected to their
respective processor power planes, while all VSS lands must be connected to the
system ground plane.
respective processor power planes, while all VSS lands must be connected to the
system ground plane.
For clean on-chip power distribution, processors include lands for all required voltage
supplies. These are listed in
supplies. These are listed in
Table 7-1
Table 7-1.
Power and Ground Lands
Power and
Ground Lands
Comments
VCC
Each VCC land must be supplied with the voltage determined by the SVID Bus signals.
Table 7-3
defines the voltage level associated with each core SVID pattern.
Note: V
CC
has a VBOOT setting of 0.0 V.
VCCPLL
Each VCCPLL land is connected to a 1.80 V supply, power the Phase Lock Loop (PLL) clock
generation circuitry. An on-die PLL filter solution is implemented within the processor.
generation circuitry. An on-die PLL filter solution is implemented within the processor.
VCCD_01
VCCD_23
VCCD_23
Each VCCD land is connected to a 1.50 V supply to provide power to the processor DDR3
interface. These supplies also power the DDR3 memory subsystem. V
interface. These supplies also power the DDR3 memory subsystem. V
CCD
may be
controlled by the SVID Bus using a VR12 controller and or a non-VR12 regulator may be
used. VCCD is the generic term for VCCD_01, VCCD_23.
used. VCCD is the generic term for VCCD_01, VCCD_23.
VTTA
VTTA lands must be supplied by a fixed 1.05 V supply.
VTTD
VTTD lands must be supplied by a fixed 1.05 V supply.
VSA
Each VSA land must be supplied with the voltage determined by the SVID Bus signals,
typically set at 0.85 V. VSA has a VBOOT setting of 0.9 V.
typically set at 0.85 V. VSA has a VBOOT setting of 0.9 V.
VSS
Ground