Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Features Summary
12
Datasheet
Dual-channel symmetric (Interleaved)
Dual-channel asymmetric
Command launch modes of 1n/2n
Partial Writes to memory using Data Mask (DM) signals
On-Die Termination (ODT)
Intel® Fast Memory Access (Intel® FMA):
Just-in-Time Command Scheduling
Command Overlap
Out-of-Order Scheduling
1.3.2
PCI Express*
The Processor PCI Express ports are fully compliant to the PCI Express Base
Specification Revision 2.0.
Specification Revision 2.0.
One 16-lane PCI Express* port intended for graphics attach.
Gen1 (2.5 GT/s) PCI Express* frequency is supported.
Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.
Hierarchical PCI-compliant configuration mechanism for downstream devices.
Traditional PCI style traffic (asynchronous snooped, PCI ordering).
PCI Express extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
PCI Express Enhanced Access Mechanism. Accessing the device configuration space
in a flat memory mapped fashion.
in a flat memory mapped fashion.
Automatic discovery, negotiation, and training of link out of reset.
Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).
Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
Virtual Channel 0:
DMI -> PCI Express Port 0
64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
above 64 GB (Bits 63:36 will always be zeros).
64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are