Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Datasheet
13
Features Summary
non-zero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
addresses above 64 GB will be dropped.
Re-issues configuration cycles that have been previously completed with the
Configuration Retry status.
Configuration Retry status.
PCI Express reference clock is 100-MHz differential clock buffered out of system
clock generator.
clock generator.
Power Management Event (PME) functions.
Static lane numbering reversal
Does not support dynamic lane reversal, as defined (optional) by the PCI
Express Base Specification.
PCI Express 1x16 configuration
Normal (1x16): PEG_RX[15:0]; PEG_TX[15:0]
Reversal (1x16): PEG_RX[0:15]; PEG_TX[0:15]
Supports Half Swing low-power/low-voltage mode.
Message Signaled Interrupt (MSI and MSI-X) messages
PEG Lanes shared with Embedded DisplayPort* (see eDP,
Section 1.3.6
).
Polarity inversion
1.3.3
Direct Media Interface (DMI)
Compliant to Direct Media Interface second generation (DMI2).
Four lanes in each direction.
2.5 GT/s point-to-point DMI interface to PCH is supported.
Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
250 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
simultaneously, for an aggregate of 2 GB/s when DMI x4.
Shares 100-MHz PCI Express reference clock.
64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
above 64 GB (Bits 63:36 will always be zeros).
64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
Supports the following traffic types to or from the PCH:
DMI -> PCI Express Port 0 write traffic
DMI -> DRAM
DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)