Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Datasheet
21
Interfaces
NOTES:
1.
1.
System memory configurations are based on availability and are subject to change.
2.
Only Raw Card D SO-DIMMs at 1066 MT/s are supported.
2.1.2
System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
command signal mode timings on the main memory interface:
tCL = CAS Latency
tRCD = Activate Command to READ or WRITE Command delay
tRP = PRECHARGE Command Period
CWL = CAS Write Latency
Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
NOTES:
1.
1.
System memory timing support is based on availability and is subject to change.
2.1.3
System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the SO-DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
Depending upon how the SO-DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
D
2
4 GB
2 Gb
256 M x 8
16
2
15/10
8
8K
F
2 GB
1 Gb
128 M x 8
16
2
14/10
8
8K
F
4 GB
2 Gb
256 M x 8
16
2
15/10
8
8K
Table 2-1. Supported SO-DIMM Module Configurations
1
Raw
Card
Version
DIMM
Capacity
DRAM
Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of Row/
Col
Address
Bits
# of
Banks
Inside
DRAM
Page
Size
Table 2-2. DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
CMD Mode
Notes
800
6
6
6
5
1n
1
1066
7
7
7
6
1n
1
8
8
8