Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Datasheet
23
Interfaces
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note:
The DRAM device technology and width may vary from one channel to the other.
2.1.3.2.2
Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start at the bottom of Channel A and stay there until the end of the highest
rank in Channel A, and then addresses continue from the bottom of Channel B to the
top. Real world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth is limited to a single channel.
addresses start at the bottom of Channel A and stay there until the end of the highest
rank in Channel A, and then addresses continue from the bottom of Channel B to the
top. Real world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth is limited to a single channel.
This mode is used when Intel Flex Memory Technology is disabled and both Channel A
and Channel B SO-DIMM connectors are populated in any order with the total amount
of memory in each channel being different.
and Channel B SO-DIMM connectors are populated in any order with the total amount
of memory in each channel being different.
2.1.4
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one SO-DIMM
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one SO-DIMM
Figure 2-3. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
CH. B
CH. A
CH. B
CH. A
CH. B
CH. A
CL
0
Top of
Memory
Memory
CL
0
CH. B
CH. A
CH.A-top
DRB
DRB
Dual Channel Interleaved
(memory sizes must match)
Dual Channel Asymmetric
(memory sizes can differ)
Top of
Memory
Memory