Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Datasheet
45
Power Management
4.2.4.4
Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
4.2.4.5
C-State Auto-Demotion
In general, deeper C-states such as Deep Power Down Technology (code named C6
state) have long latencies and have higher energy entry/exit costs. The resulting
performance and energy penalties become significant when the entry/exit frequency of
a deeper C-state is high. Therefore incorrect or inefficient usage of deeper C-states
have a negative impact on battery life. In order to increase residency and improve
battery life in deeper C-states, the processor supports C-state auto-demotion.
state) have long latencies and have higher energy entry/exit costs. The resulting
performance and energy penalties become significant when the entry/exit frequency of
a deeper C-state is high. Therefore incorrect or inefficient usage of deeper C-states
have a negative impact on battery life. In order to increase residency and improve
battery life in deeper C-states, the processor supports C-state auto-demotion.
There are two C-State auto-demotion options:
Deep Power Down Technology (code named C6 state) to C3
Deep Power Down Technology (code named C6 state)/C3 To C1
The decision to demote a core from Deep Power Down Technology (code named C6
state) to C3 or C3/Deep Power Down Technology (code named C6 state) to C1 is based
on each cores immediate residency history. Upon each core Deep Power Down
Technology (code named C6 state) request, the core C-state is demoted to C3 or C1
until a sufficient amount of residency has been established. At that point, a core is
allowed to go into C3/Deep Power Down Technology (code named C6 state). Each
option can be run concurrently or individually.
state) to C3 or C3/Deep Power Down Technology (code named C6 state) to C1 is based
on each cores immediate residency history. Upon each core Deep Power Down
Technology (code named C6 state) request, the core C-state is demoted to C3 or C1
until a sufficient amount of residency has been established. At that point, a core is
allowed to go into C3/Deep Power Down Technology (code named C6 state). Each
option can be run concurrently or individually.
This feature is disabled by default.
4.2.5
Package C-States
The processor supports C0, C1/C1E, C3, and Deep Power Down Technology (code
named C6 state) package idle power states. The following is a summary of the general
rules for package C-state entry. These apply to all package C-states unless specified
otherwise:
named C6 state) package idle power states. The following is a summary of the general
rules for package C-state entry. These apply to all package C-states unless specified
otherwise:
A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
amongst all cores.
A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
core idle power states and the status of the platform components.
Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
The platform may allow additional power savings to be realized in the processor.
Refer to
Section 4.3.2.2
For package C-states, the processor is not required to enter C0 before entering any
other C-state.
other C-state.