Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
101
The SMBCLK (SMBus Clock) signal is an input clock to the system management logic which is required for operation of
the system management features of the Pentium® III Xeon™ processor at 700 MHz and 900 MHz. This clock is
asynchronous to other clocks to the processor.
the system management features of the Pentium® III Xeon™ processor at 700 MHz and 900 MHz. This clock is
asynchronous to other clocks to the processor.
10.1.51 SMBDAT (I/O)
The SMBDAT (SMBus DATA) signal is the data signal for the SMBus. This signal provides the single-bit mechanism for
transferring data between SMBus devices.
transferring data between SMBus devices.
10.1.52 SMI# (I)
The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System
Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
10.1.53 STPCLK# (I)
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop Grant state. The
processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core
units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in
Stop Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core
units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in
Stop Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
10.1.54 TCK (I)
The TCK (Test Clock) signal provides the clock input for processor Test Bus (also known as the Test Access Port).
10.1.55 TDI (I)
The TDI (Test Data In) signal transfers serial test data into the processor. TDI provides the serial input needed for TAP
support.
support.
10.1.56 TDO (O)
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO provides the serial output needed for
TAP support.
TAP support.
10.1.57 TEST_2.5_[A23, A62, B27] (I)
The TEST_2.5_A62 signal must be connected to a 2.5V power source through a 1-10K
Ω
resistor for proper processor
operation.
10.1.58 THERMTRIP# (O)
This pin indicates a thermal overload condition (thermal trip). The processor protects itself from catastrophic overheating
by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there
are no false trips. The processor will immediately stop all execution when the junction temperature exceeds approximately
135°C. This is signaled to the system by the THERMTRIP# pin. Once activated, the signal remains latched, and the
processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. Once the die
temperature drops below the trip level, a RESET# pulse will reinitialize the processor and execution will continue at the
reset vector. If the temperature has not dropped below the trip level, the processor will continue to drive THERMTRIP#
and remain stopped regardless of the state of RESET#.
The system designer should not act upon THERMTRIP# until after the RESET# input is de-asserted. Until this time, the
THERMTRIP# output is indeterminate.
by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there
are no false trips. The processor will immediately stop all execution when the junction temperature exceeds approximately
135°C. This is signaled to the system by the THERMTRIP# pin. Once activated, the signal remains latched, and the
processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. Once the die
temperature drops below the trip level, a RESET# pulse will reinitialize the processor and execution will continue at the
reset vector. If the temperature has not dropped below the trip level, the processor will continue to drive THERMTRIP#
and remain stopped regardless of the state of RESET#.
The system designer should not act upon THERMTRIP# until after the RESET# input is de-asserted. Until this time, the
THERMTRIP# output is indeterminate.
10.1.59 TMS (I)
The TMS (Test Mode Select) signal is a TAP support signal used by debug tools.