Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
102
10.1.60 TRDY# (I)
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit
writeback data transfer. TRDY# must connect the appropriate pins of all processor system bus agents.
writeback data transfer. TRDY# must connect the appropriate pins of all processor system bus agents.
10.1.61 TRST# (I)
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The processor self-resets during power on;
therefore, it is not necessary to drive this signal during power on reset.
therefore, it is not necessary to drive this signal during power on reset.
10.1.62 VID_L2[4:0], VID_CORE[4:0] (O)
The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not
signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations
on the processor. See Table 2 for definitions of these pins. The power supply must supply the voltage that is requested by
these pins, or disable itself. See section 3.9 for the maximum rating for these signals.
signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations
on the processor. See Table 2 for definitions of these pins. The power supply must supply the voltage that is requested by
these pins, or disable itself. See section 3.9 for the maximum rating for these signals.
10.1.63 VIN_SENSE
VIN_SENSE (formerly called CPU_SENSE) is routed from edge-connector pin A56 to the VCC_CORE power plane.
VIN_SENSE provides remote sensing capabilities for the voltage seen at the input of the OCVR.
NOTE: Pentium® III Xeon™ processor at 700 MHz and 900 MHz support either +2.8V, +5V or +12V VCC_CORE
voltages depending on the version of OCVR. Therefore, any sensing logic must be capable of tolerating the
selected VCC_CORE voltage (+2.8/+5V/+12V).
VIN_SENSE provides remote sensing capabilities for the voltage seen at the input of the OCVR.
NOTE: Pentium® III Xeon™ processor at 700 MHz and 900 MHz support either +2.8V, +5V or +12V VCC_CORE
voltages depending on the version of OCVR. Therefore, any sensing logic must be capable of tolerating the
selected VCC_CORE voltage (+2.8/+5V/+12V).
10.1.64 WP (I)
WP (Write Protect) can be used to write protect the scratch EEPROM. A high level write-protects the scratch EEPROM.
10.2 Signal Summaries
The following tables list attributes of the processor input, output, and I/O signals.
Table 60. Output Signals
Name Active
Level Clock
Signal
Group
FERR# Low Asynch
CMOS
Output
IERR# Low Asynch
CMOS
Output
PRDY# Low BCLK
AGTL+
Output
SMBALERT# Low
Asynch SMBus
Output
TDO High TCK TAP
Output
THERMTRIP# Low
Asynch CMOS
Output
VID_CORE[4:0] High
Asynch
Power/Other
VID_L2[4:0] High
Asynch Power/Other
CPU_SENSE High
Asynch
Power/Other
L2_SENSE
High
Asynch
Power/Other
OCVR_OK High
Asynch Power/Other