Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
100
Table 59. Description of SELFSB pins
processor
Pin Location
Pin Name
Functionality
A7 SELFSB1
Output,
Frequency
Detect
Detect
Pentium® III Xeon™
processor at 700 MHz and
900 MHz
processor at 700 MHz and
900 MHz
A9 SELFSB0
Input,
Frequency
Selection.
Frequency
Selection.
A7 Vss None
Pentium® III Xeon™
processor at 500 MHz and
550 MHz & Pentium® II
Xeon™ processor
processor at 500 MHz and
550 MHz & Pentium® II
Xeon™ processor
A9 Reserved
None
SELFSB1: Output, (Frequency Detect).
100 MHz = GND.
SELFSB0:
Pentium® III Xeon™ processor at 500 MHz and 550 MHz: Not used..
Pentium® III Xeon™ processor at 700 MHz and 900 MHz: Input; (Frequency Select).
100 MHz= N/C or pull up to 2.5 V
Α9
SE LF SB 0
Α7
SE LF SB 1
2.5 V
3.3ΚΩ
100M H z _SEL
J umpe rs
(f or de bug onl y)
J umpe rs
(f or de bug onl y)
8.2ΚΩ
15ΚΩ
MC H
C K 133
V a = 2.15 V
V c = 1.41 V
2.5 V
1ΚΩ
Processo r
Co re
Figure 43. Recommended circuit for frequency auto detection
10.1.48 SLP# (I)
The SLP# (Sleep) signal, when asserted in Stop Grant state, causes processors to enter the Sleep state. During Sleep
state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still
operating. processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of
the SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core units.
state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still
operating. processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of
the SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core units.
10.1.49 SMBALERT# (O)
SMBALERT# is an asynchronous interrupt line associated with the SMBus Thermal Sensor device.
10.1.50 SMBCLK (I)