Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
PROCESSOR FEATURES
42
2. Auto H AL T Power Down State
BCL K running.
Snoops and interrupts allowed.
Snoops and interrupts allowed.
HA L T Instruction and
HA L T Bus Cycle Generated
HA L T Bus Cycle Generated
INIT#, BINIT#, INTR, NM I,
SM I#, RESET#
SM I#, RESET#
1. Nor mal State
Normal execution.
STPCL K #
A sserted
A sserted
STPCL K #
De-asserted
De-asserted
3. Stop Gr ant State
BCL K running.
Snoops and interrupts allowed.
Snoops and interrupts allowed.
SL P#
A sserted
A sserted
SL P#
De-asserted
De-asserted
5. Sleep State
BCL K running.
No snoops or interrupts allowed.
No snoops or interrupts allowed.
4. H AL T /Grant Snoop State
BCL K running.
Service snoops to caches.
Service snoops to caches.
Snoop Event Occurs
Snoop Event Serviced
Snoop
Event
Occurs
Event
Occurs
Snoop
Event
Serviced
Event
Serviced
STPC
L K# A
sserted
STPC
L K# D
e-asser
ted
P6CB757a
P6CB757b
P6CB757b
Figure 15. Stop Clock State Machine
5.1.3
STOP-GRANT STATE — STATE 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted. The processor will
issue a Stop-Grant Transaction Cycle. Exit latency from this mode is 10 BLCK periods after the STPCLK#
signal is de-asserted.
issue a Stop-Grant Transaction Cycle. Exit latency from this mode is 10 BLCK periods after the STPCLK#
signal is de-asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the
level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other
input pins on the system bus should be driven to the inactive state.
level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other
input pins on the system bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be
serviced by software upon exit from Stop-Grant state.
serviced by software upon exit from Stop-Grant state.
FLUSH# will not be serviced during Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop Grant state.
A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal.
A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop phase on the
system bus. A transition to the Sleep state will occur with the assertion of the SLP# signal.
system bus. A transition to the Sleep state will occur with the assertion of the SLP# signal.
While in the Stop Grant State, all other interrupts will be latched by the processor, and only serviced when the
processor returns to the Normal State.
processor returns to the Normal State.
5.1.4
HALT/GRANT SNOOP STATE — STATE 4
The processor will respond to snoop phase transactions (initiated by ADS#) on the system bus while in Stop-
Grant state or in Auto HALT Power Down state. When a snoop transaction is presented upon the system bus,
the processor will enter the HALT/Grant Snoop state. The processor will stay in this state until the snoop on
the system bus has been serviced (whether by the processor or another agent on the system bus). After the
snoop is serviced, the processor will return to the Stop-Grant state or Auto HALT Power Down state, as
appropriate.
Grant state or in Auto HALT Power Down state. When a snoop transaction is presented upon the system bus,
the processor will enter the HALT/Grant Snoop state. The processor will stay in this state until the snoop on
the system bus has been serviced (whether by the processor or another agent on the system bus). After the
snoop is serviced, the processor will return to the Stop-Grant state or Auto HALT Power Down state, as
appropriate.