Intel III Xeon 800 MHz 80526KZ800256 User Manual

 

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The Sleep state is a very low power state in which the processor maintains its context, maintains the PLL, and 
has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-
Grant state (verified by the termination of the Stop-Grant Bus transaction cycle), the SLP# pin can be 
asserted, causing the processor to enter the Sleep state.  The system must wait 100 BCLK cycles after the 
completion of the Stop-Grant Bus cycle before SLP# is asserted. For an MP system, all processors must 
complete the Stop Grant bus cycle before the subsequent 100 BCLK wait and assertion of SLP# can occur. 
The processor is in Sleep state 10 BCLKs after the assertion of the SLP# pin. The latency to exit the Sleep 
state is 10 BCLK cycles. The SLP# pin is not recognized in the Normal, or Auto HALT States. Snoop events 
that occur during a transition into or out of Sleep state will cause unpredictable behavior. Therefore, 
transactions should be blocked by system logic during these transitions. 
 
In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals 
immediately after the assertion of the SLP# pin (one exception is RESET# which causes the processor to re-
initialize itself). The system core logic must detect these events and de-assert the SLP# signal (and 
subsequently de-assert the STPCLK# signal for interrupts) for the processor to correctly interpret any bus 
transaction or signal transition. Once in the Sleep state, the SLP# pin can be de-asserted if another 
asynchronous event occurs. 
 
No transitions or assertions of signals are allowed on the system bus while the processor is in Sleep state. 
Any transition on an input signal (with the exception of SLP# or RESET#) before the processor has returned to 
Stop Grant state will result in unpredictable behavior. 
 
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the 
RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop Grant State. 
If RESET# is driven active while the processor is in the Sleep State and normal operation is desired, the SLP# 

and STPCLK# should be de-asserted immediately after RESET# is asserted

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During Auto HALT Power Down and Stop-Grant states, the processor will continue to process the snoop 
phase of a system bus cycle. The PICCLK signal should not be removed during the Auto HALT Power Down 
or Stop-Grant states. When the processor is in the Sleep state, it will not respond to interrupts or snoop 
transactions. PICCLK can be removed during the Sleep state. 
 
The processor will not enter any low power states until all internal queues for the second level cache are 
empty. When re-entering Normal state, the processor will resume processing external cache requests as soon 
as new requests are encountered.  

5.2  System Management Bus (SMBus) Interface 
 

The processor includes an SMBus interface that allows access to several processor features, including two 
memory components (referred to as the processor Information ROM and the Scratch EEPROM) and a thermal 
sensor on the processor substrate. These devices and their features are described below. 
 
The processor SMBus implementation uses the clock and data signals of the SMBus specification. It does not 
implement the SMBSUS# signals.