Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
97
Figure 42. PWRGD Implementation
10.1.41 REQ[4:0]# (I/O)
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents. They
are asserted by the current bus owner over two clock cycles to define the currently active transaction type.
are asserted by the current bus owner over two clock cycles to define the currently active transaction type.
+5V
OCVR_EN
OCVR
OCVR_OK
OCVR_OK
CPU_PWR_GD
OCVR_EN
5V
PWR_GD_PS
Vcc_smb(3.3V)
5V
CPU_PWRGD
Other PS’s,
VRMs, OCVRs
with
open-drain
PWR_GDs
PWR_GDs
VRM
PWRGD
OUTEN
CPU_RESET#
Delay
Reset Logic
3V->5V
buffer
(7408)
buffer
(7408)
3.3V
Pull-up for Pentium® III Xeon™ Processor
3.3V
Processor
Core