Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
98
10.1.42 RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2 caches without writing
back any of their contents. RESET# must remain active for one microsecond for a "warm" reset; for a power-on reset,
RESET# must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted; until this
de-assertion of RESET# occurs, all outputs from the processor are indeterminate unless otherwise specified. On
observing active RESET#, all processor system bus agents will de-assert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the
back any of their contents. RESET# must remain active for one microsecond for a "warm" reset; for a power-on reset,
RESET# must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted; until this
de-assertion of RESET# occurs, all outputs from the processor are indeterminate unless otherwise specified. On
observing active RESET#, all processor system bus agents will de-assert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the
Pentium II Processor Developer’s Manual
.
The processor may have its outputs tri-stated via power-on configuration. Otherwise, if INIT# is sampled active during the
active-to-inactive transition of RESET#, the processor will execute its Built-In Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the reset-vector (default 0_FFFF_FFF0h). RESET# must connect
the appropriate pins of all processor system bus agents.
10.1.43 RP# (I/O)
The RP# (Request Parity) signal is driven by the request initiator, and provides parity protection on ADS# and REQ[4:0]#.
It must connect the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number
of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
It must connect the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number
of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
10.1.44 RS[2:0]# (I)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for completion of the
current transaction), and must connect the appropriate pins of all processor system bus agents.
current transaction), and must connect the appropriate pins of all processor system bus agents.
10.1.45 RSP# (I)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for completion of the current
transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this
indicates it is not being driven by any agent guaranteeing correct parity
transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this
indicates it is not being driven by any agent guaranteeing correct parity
.
10.1.46 SA[2:0] (I)
The SA (Select Address) pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain
unique addresses on the SMBus in a system with multiple processors. To set an SA line high, a pull-up resistor should be
used that is no larger than 1K
unique addresses on the SMBus in a system with multiple processors. To set an SA line high, a pull-up resistor should be
used that is no larger than 1K
Ω
. To set an SA line as low, the pin can be left unconnected. SA2 can also be tri-stated to
define additional addresses for the thermal sensor. A tri-state or “Z” state on this pin is achieved by leaving this pin
unconnected.
unconnected.
Of the addresses broadcast across the SMBus, the memory components claim those of the form “1010XXYZb”. The “XX”
and “Y” bits are used to enable the devices on the cartridge at adjacent addresses. The Y bit is hard-wired on the
cartridge to VSS (‘0’) for the Scratch EEPROM and pulled to VCCSMB (‘1’) for the processor Information ROM. The “XX”
bits are defined by the processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled
down weakly (10 k ) on the cartridge to ensure that the memory components are in a known state in systems which do
not support the SMBus, or only support a partial implementation. The “Z” bit is the read/write bit for the serial bus
transaction.
The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form “0011XXXZb”,
“1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, includes a Hi-Z state for one address pin
(SA2), and therefore supports 6 unique resulting addresses. The ability of the system to drive this pin to a Hi-Z state is
dependent on the baseboard implementation (The pin must be left floating). The system should drive SA1 and SA0, and
will be pulled low (if not driven) by the 10 k pull-down resistor on the processor substrate. Driving these signals to a Hi-Z
state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding, thus
timing out or hanging the SMBus. As before, the “Z” bit is the read/write bit for the serial bus transaction. For more
information on the usage of these pins, see section 5.2.7.
and “Y” bits are used to enable the devices on the cartridge at adjacent addresses. The Y bit is hard-wired on the
cartridge to VSS (‘0’) for the Scratch EEPROM and pulled to VCCSMB (‘1’) for the processor Information ROM. The “XX”
bits are defined by the processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled
down weakly (10 k ) on the cartridge to ensure that the memory components are in a known state in systems which do
not support the SMBus, or only support a partial implementation. The “Z” bit is the read/write bit for the serial bus
transaction.
The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form “0011XXXZb”,
“1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, includes a Hi-Z state for one address pin
(SA2), and therefore supports 6 unique resulting addresses. The ability of the system to drive this pin to a Hi-Z state is
dependent on the baseboard implementation (The pin must be left floating). The system should drive SA1 and SA0, and
will be pulled low (if not driven) by the 10 k pull-down resistor on the processor substrate. Driving these signals to a Hi-Z
state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding, thus
timing out or hanging the SMBus. As before, the “Z” bit is the read/write bit for the serial bus transaction. For more
information on the usage of these pins, see section 5.2.7.