Intel 200 MHz FV8050366200 User Manual

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5/23/97 10:47 AM    24318502.DOC

RESET

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RESET forces the Pentium processor with MMX technology to begin execution at
a known state. All the Pentium processor with MMX technology internal caches
will be invalidated upon the RESET. Modified lines in the data cache are not
written back. FLUSH# and INIT are sampled when RESET transitions from high to
low to determine if tristate test mode or checker mode will be entered, or if Built-In
Self-Test (BIST) will be run.

SCYC

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The split cycle output is asserted during misaligned LOCKed transfers to indicate
that more than two cycles will be locked together. This signal is defined for locked
cycles only. It is undefined for cycles which are not locked.

SMI#

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The system management interrupt causes a system management interrupt
request to be latched internally. When the latched SMI# is recognized on an
instruction boundary, the processor enters System Management Mode.

SMIACT#

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An active system management interrupt active output indicates that the
processor is operating in System Management Mode.

STPCLK#

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Assertion of the stop clock input signifies a request to stop the internal clock of
the Pentium processor with MMX technology, thereby causing the core to
consume less power. When the CPU recognizes STPCLK#, the processor will
stop execution on the next instruction boundary, unless superseded by a higher
priority interrupt, and generate a stop grant acknowledge cycle. When STPCLK#
is asserted, the Pentium processor with MMX technology will still respond to
interprocessor and external snoop requests.

TCK

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The testability clock input provides the clocking function for the Pentium
processor with MMX technology boundary scan in accordance with the IEEE
Boundary Scan interface (Standard 1149.1). It is used to clock state information
and data into and out of the Pentium processor with MMX technology during
boundary scan.

TDI

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The test data input is a serial input for the test logic. TAP instructions and data
are shifted into the Pentium processor with MMX technology on the TDI pin on the
rising edge of TCK when the TAP controller is in an appropriate state.

TDO

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The test data output is a serial output of the test logic. TAP instructions and data
are shifted out of the Pentium processor with MMX technology on the TDO pin on
TCK’s falling edge when the TAP controller is in an appropriate state.

TMS

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The value of the test mode select input signal sampled at the rising edge of TCK
controls the sequence of TAP controller state changes.

TRST#

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When asserted, the test reset input allows the TAP controller to be
asynchronously initialized.

V

CC2

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The Pentium processor with MMX technology has 25 2.8V power inputs.

V

CC3

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The Pentium processor with MMX technology has 28 3.3V power inputs.

V

CC2

DET#

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 detect is used in flexible motherboard implementations to configure the

voltage output set-point appropriately for the V

CC2

 inputs of the processor.