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Intel 200 MHz FV8050366200 User Manual

Product codes
FV8050366200
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
E
24
5/23/97 10:47 AM    24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
2.4.
Pin Reference Tables
Table 4.  Output Pins
Name
Active Level
When Floated
ADS# 
(1)
Low
Bus Hold, BOFF#
ADSC#
Low
Bus Hold, BOFF#
APCHK#
Low
BE7#-BE4#
Low
Bus Hold, BOFF#
BREQ
High
CACHE#
 (1)
Low
Bus Hold, BOFF#
D/P#
 (2)
N/A
FERR#
 (2)
Low
HIT#
 (1)
Low
HITM#
 (1, 3)
Low
HLDA
 (1)
High
IERR#
Low
LOCK#
 (1)
Low
Bus Hold, BOFF#
M/IO#
 (1)
, D/C#
 (1)
, W/R#
 (1)
N/A
Bus Hold, BOFF#
PCHK#
Low
BP3-2, PM1/BP1, PM0/BP0
High
PRDY
High
PWT, PCD
High
Bus Hold, BOFF#
SCYC
 (1)
High
Bus Hold, BOFF#
SMIACT#
Low
TDO
N/A
All states except Shift-DR and Shift-IR
V
CC
2DET#
Low
NOTES:
All output and input/output pins are floated during tristate test mode (except IERR#).
1.
These are I/O signals when two Pentium
®
 processor with MMX™ technology are operating in dual processing mode.
2.
These signals are undefined when the processor is configured as a Dual processor.
3.
M# pin has an internal pull-up resistor.