Intel 200 MHz FV8050366200 User Manual
Product codes
FV8050366200
E
PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
23
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
Table 2. Quick Pin Reference (Cont’d)
Symbol
Type
Name and Function
V
SS
I
The Pentium processor with MMX technology has 53 ground inputs.
W/R#
O
Write/read is one of the primary bus cycle definition pins. It is driven valid in the
same clock as the ADS# signal is asserted. W/R# distinguishes between write
and read cycles.
same clock as the ADS# signal is asserted. W/R# distinguishes between write
and read cycles.
WB/WT#
I
The write back/write through input allows a data cache line to be defined as
write back or write through on a line-by-line basis. As a result, it determines
whether a cache line is initially in the S or E state in the data cache.
write back or write through on a line-by-line basis. As a result, it determines
whether a cache line is initially in the S or E state in the data cache.
Core and bus frequencies can be set according to Table 3 below. Each Pentium processor with MMX technology
specified to operate within a single bus-to-core ratio and a specific minimum to maximum bus frequency range
(corresponding to a minimum to maximum core frequency range). Operation in other bus-to-core ratios or
outside the specified operating frequency range is not supported. For example, the 166 MHz Pentium processor
with MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2/5 bus-to-core
ratio; it does not support the 1/3, 1/2, or 2/3 bus-to-core ratios. Table 3 clarifies and summarizes these
specifications.
specified to operate within a single bus-to-core ratio and a specific minimum to maximum bus frequency range
(corresponding to a minimum to maximum core frequency range). Operation in other bus-to-core ratios or
outside the specified operating frequency range is not supported. For example, the 166 MHz Pentium processor
with MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2/5 bus-to-core
ratio; it does not support the 1/3, 1/2, or 2/3 bus-to-core ratios. Table 3 clarifies and summarizes these
specifications.
Table 3. Bus Frequency Selections
BF1
BF0
Bus/Core Ratio
Max Bus/Core
Frequency (MHz)
Min Bus/Core
Frequency (MHz)
0
1
1/3
66/200
33/100
0
0
2/5
66/166
33/83
1
0
1/2
(1, 2)
N/A
(2)
N/A
(2)
1
1
2/7
66/233
33/117
NOTES:
1.
This is the default bus to core ratio for the Pentium
®
processor with MMX™ technology. If the BF pins are left floating, the
processor will be configured for the 1/2 bus to core frequency ratio.
2.
Currently, there are no products that support these bus fractions.