Intel 200 MHz FV8050366200 User Manual
Product codes
FV8050366200
PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
E
26
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
Table 6. Input/Output Pins
(1)
Name
Active
Level
When Floated
Qualified
(when an input)
Internal
Resistor
A31-A3
N/A
Address Hold, Bus Hold, BOFF#
EADS#
AP
N/A
Address Hold, Bus Hold, BOFF#
EADS#
BE3#-BE0#
Low
Address Hold, Bus Hold, BOFF#
RESET
Pull-down
(2)
D63-D0
N/A
Bus Hold, BOFF#
BRDY#
DP7-DP0
N/A
Bus Hold, BOFF#
BRDY#
DPEN#
low
RESET
Pull-up
PICD0
N/A
Pull-up
PICD1
N/A
Pull-down
NOTES:
1.
All output and input/output pins are floated during tristate test mode (except TDO, IERR# and TDO).
2.
BE3#-BE0# have Pull-downs during RESET only.
Table 7. Inter-Processor Input/Output Pins
Name
Active Level
Internal Resistor
PHIT#
Low
Pull-up
PHITM#
Low
Pull-up
PBGNT#
Low
Pull-up
PBREQ#
Low
Pull-up
NOTES:
For proper inter-processor operation, the system cannot load these signals.