Intel 200 MHz FV8050366200 User Manual
Product codes
FV8050366200
E
PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
27
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
2.5.
Pin Grouping According to Function
Table 8 organizes the pins with respect to their function.
Table 8. Pin Functional Grouping
Function
Pins
Clock
CLK
Initialization
RESET, INIT, BF1–BF0
Address Bus
A31-A3, BE7#–BE0#
Address Mask
A20M#
Data Bus
D63-D0
Address Parity
AP, APCHK#
APIC Support
PICCLK, PICD0-1
Data Parity
DP7-DP0, PCHK#, PEN#
Internal Parity Error
IERR#
System Error
BUSCHK#
Bus Cycle Definition
M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK#
Bus Control
ADS#, ADSC#, BRDY#, BRDYC#, NA#
Page Cacheability
PCD, PWT
Cache Control
KEN#, WB/WT#
Cache Snooping/Consistency
AHOLD, EADS#, HIT#, HITM#, INV
Cache Flush
FLUSH#
Write Ordering
EWBE#
Bus Arbitration
BOFF#, BREQ, HOLD, HLDA
Dual Processing Private Bus Control
PBGNT#, PBREQ#, PHIT#, PHITM#
Interrupts
INTR, NMI
Floating-Point Error Reporting
FERR#, IGNNE#
System Management Mode
SMI#, SMIACT#
TAP Port
TCK, TMS, TDI, TDO, TRST#
Breakpoint/Performance Monitoring
PM0/BP0, PM1/BP1, BP3-2
Power Management
STPCLK#
Miscellaneous Dual Processing
CPUTYP, D/P#
Debugging
R/S#, PRDY
Voltage Detection
VCC2DET#