Intel 200 MHz FV8050366200 User Manual
Product codes
FV8050366200
E
PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
5
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
For a more detailed description of the Pentium
processor family products, please refer to the
processor family products, please refer to the
Pentium
®
Processor Family Developer’s Manual
(Order Number 241428).
1.1.
Pentium® Processor Family
Architecture
Architecture
The application instruction set of the Pentium
processor family includes the complete Intel486
processor family instruction set with extensions to
accommodate some of the additional functionality of
the Pentium processors. All application software
written for the Intel386 and Intel486 family
microprocessors will run on the Pentium processors
without modification. The on-chip memory
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of
processors.
processor family includes the complete Intel486
processor family instruction set with extensions to
accommodate some of the additional functionality of
the Pentium processors. All application software
written for the Intel386 and Intel486 family
microprocessors will run on the Pentium processors
without modification. The on-chip memory
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of
processors.
The Pentium processors implement several
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one clock,
or one floating-point instruction (under certain
circumstances, two floating-point instructions) in one
clock.
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one clock,
or one floating-point instruction (under certain
circumstances, two floating-point instructions) in one
clock.
Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch code
in a linear fashion, and one that prefetches code
according to the BTB so the needed code is almost
always prefetched before it is needed for execution.
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch code
in a linear fashion, and one that prefetches code
according to the BTB so the needed code is almost
always prefetched before it is needed for execution.
The floating-point unit has been completely
redesigned over the Intel486 processor. Faster
algorithms provide up to 10X speed-up for common
operations including add, multiply and load.
redesigned over the Intel486 processor. Faster
algorithms provide up to 10X speed-up for common
operations including add, multiply and load.
Pentium processors include separate code and data
caches are integrated on-chip to meet performance
goals. Each cache has a 32-byte line size. Each
cache has a dedicated Translation Lookaside Buffer
(TLB) to translate linear addresses to physical
addresses. The data cache is configurable to be
write back or write through on a line-by-line basis and
follows the MESI protocol. The data cache tags are
triple ported to support two data transfers and an
caches are integrated on-chip to meet performance
goals. Each cache has a 32-byte line size. Each
cache has a dedicated Translation Lookaside Buffer
(TLB) to translate linear addresses to physical
addresses. The data cache is configurable to be
write back or write through on a line-by-line basis and
follows the MESI protocol. The data cache tags are
triple ported to support two data transfers and an
inquire cycle in the same clock. The code cache is
an inherently write-protected cache. The code cache
tags are multi-ported to support snooping. Individual
pages can be configured as cacheable or non-
cacheable by software or hardware. The caches can
be enabled or disabled by software or hardware.
an inherently write-protected cache. The code cache
tags are multi-ported to support snooping. Individual
pages can be configured as cacheable or non-
cacheable by software or hardware. The caches can
be enabled or disabled by software or hardware.
The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate. Burst
read and burst write back cycles are supported by
the Pentium processors. In addition, bus cycle
pipelining has been added to allow two bus cycles to
be in progress simultaneously. The Pentium
processors’ Memory Management Unit contains
optional extensions to the architecture which allow 4-
Kbyte and 4-Mbyte page sizes.
bus to 64 bits to improve the data transfer rate. Burst
read and burst write back cycles are supported by
the Pentium processors. In addition, bus cycle
pipelining has been added to allow two bus cycles to
be in progress simultaneously. The Pentium
processors’ Memory Management Unit contains
optional extensions to the architecture which allow 4-
Kbyte and 4-Mbyte page sizes.
The Pentium processors have added significant data
integrity and error detection capability. Data parity
checking is still supported on a byte-by-byte basis.
Address parity checking and internal parity checking
features have been added along with a new
exception, the machine check exception.
integrity and error detection capability. Data parity
checking is still supported on a byte-by-byte basis.
Address parity checking and internal parity checking
features have been added along with a new
exception, the machine check exception.
As more and more functions are integrated on chip,
the complexity of board level testing is increased. To
address this, the Pentium processors have increased
test and debug capability. The Pentium processors
implement IEEE Boundary Scan (Standard 1149.1).
In addition, the Pentium processors have specified 4
breakpoint pins that correspond to each of the debug
registers and externally indicate a breakpoint match.
Execution tracing provides external indications when
an instruction has completed execution in either of
the two internal pipelines, or when a branch has been
taken.
the complexity of board level testing is increased. To
address this, the Pentium processors have increased
test and debug capability. The Pentium processors
implement IEEE Boundary Scan (Standard 1149.1).
In addition, the Pentium processors have specified 4
breakpoint pins that correspond to each of the debug
registers and externally indicate a breakpoint match.
Execution tracing provides external indications when
an instruction has completed execution in either of
the two internal pipelines, or when a branch has been
taken.
System Management Mode (SMM) has been
implemented along with some extensions to the SMM
architecture. Enhancements to the virtual 8086 mode
have been made to increase performance by
reducing the number of times it is necessary to trap
to a virtual 8086 monitor.
implemented along with some extensions to the SMM
architecture. Enhancements to the virtual 8086 mode
have been made to increase performance by
reducing the number of times it is necessary to trap
to a virtual 8086 monitor.
Figure 1 shows a block diagram of the Pentium
processor with MMX technology as a representative
of the Pentium processor family.
processor with MMX technology as a representative
of the Pentium processor family.
The block diagram shows the two instruction
pipelines, the "u" pipe and the "v" pipe. The u-pipe
can execute all integer and floating-point instructions.
The v-pipe can execute simple integer instructions
and the FXCH floating-point instructions.
pipelines, the "u" pipe and the "v" pipe. The u-pipe
can execute all integer and floating-point instructions.
The v-pipe can execute simple integer instructions
and the FXCH floating-point instructions.