Intel 200 MHz FV8050366200 User Manual
Product codes
FV8050366200
PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
E
6
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
Branch
Target
Buffer
Code Cache
16 KBytes
ROM
Control Unit
Generate
Address
Generate
Data Cache
16 KBytes
128
TLB
TLB
Prefetch
Address
Prefetch Buffers
Instruction Decode
Instruction
Pointer
Integer Register File
ALU
Barrel Shifter
32
32
32
32
32
32
Page
Unit
Bus
Unit
Unit
32-Bit
Address
Bus
Control
64-Bit
Data
Bus
32-Bit
Addr.
Bus
Addr.
Bus
64
Control
Register File
Add
Multiply
Divide
Floating
Point
Unit
Control
80
80
Address
(U Pipeline)
(V Pipeline)
(U Pipeline)
(V Pipeline)
ALU
Branch Verif.
& Target Addr
32
64-Bit
Data
Bus
MMX
TM
Unit
V-Pipeline
Connection
Connection
U-Pipeline
Connection
Connection
Data
Control
APIC
Control
DP
Logic
Figure 1. Pentium
®
Processor with MMX™ Technology Block Diagram
The separate code and data caches are shown. The
data cache has two ports, one for each of the two
pipes (the tags are triple ported to allow simultaneous
inquire cycles). The data cache has a dedicated
Translation Lookaside Buffer (TLB) to translate linear
addresses to the physical addresses used by the
data cache.
data cache has two ports, one for each of the two
pipes (the tags are triple ported to allow simultaneous
inquire cycles). The data cache has a dedicated
Translation Lookaside Buffer (TLB) to translate linear
addresses to the physical addresses used by the
data cache.
The code cache, branch target buffer and prefetch
buffers are responsible for getting raw instructions
into the execution units of the Pentium processor.
Instructions are fetched from the code cache or from
the external bus. Branch addresses are remembered
by the branch target buffer. The code cache TLB
translates linear addresses to physical addresses
used by the code cache.
buffers are responsible for getting raw instructions
into the execution units of the Pentium processor.
Instructions are fetched from the code cache or from
the external bus. Branch addresses are remembered
by the branch target buffer. The code cache TLB
translates linear addresses to physical addresses
used by the code cache.
The decode unit decodes the prefetched instructions
so the Pentium processors can execute the
so the Pentium processors can execute the
instruction. The control ROM contains the microcode
which controls the sequence of operations that must
be performed to implement the Pentium processor
architecture. The control ROM unit has direct control
over both pipelines.
which controls the sequence of operations that must
be performed to implement the Pentium processor
architecture. The control ROM unit has direct control
over both pipelines.
The Pentium processors contain a pipelined floating-
point unit that provides a significant floating-point
performance advantage over previous generations of
processors.
point unit that provides a significant floating-point
performance advantage over previous generations of
processors.
Symmetric dual processing in a system is supported
with two Pentium processors. The two processors
appear to the system as a single Pentium processor.
Operating systems with dual processing support
properly schedule computing tasks between the two
processors. This scheduling of tasks is transparent
to software applications and the end-user. Logic built
into the processors support a "glueless" interface for
with two Pentium processors. The two processors
appear to the system as a single Pentium processor.
Operating systems with dual processing support
properly schedule computing tasks between the two
processors. This scheduling of tasks is transparent
to software applications and the end-user. Logic built
into the processors support a "glueless" interface for