Intel 200 MHz FV8050366200 User Manual

E

7

5/23/97 10:47 AM    24318502.DOC

easy system design. Through a private bus, the two
Pentium processors arbitrate for the external bus and
maintain cache coherency. Dual processing is
supported in a system only if both processors are
operating at identical core and bus frequencies.

In this document, in order to distinguish between two
Pentium processors in dual processing mode, one
processor will be designated as the "Primary"
processor and the other as the "Dual" processor.

The Pentium processors are produced on the
enhanced 0.35 µm CMOS process which allows high
device density and lower power dissipation. In
addition to the SMM features described above, the
Pentium processor supports clock control. When the
clock to the Pentium processor is stopped, power
dissipation is virtually eliminated. The combination of
these improvements makes the Pentium processor a
good choice for energy-efficient desktop designs.

The Pentium processor supports fractional bus
operation. This allows the internal processor core to
operate at high frequencies, while communicating
with the external bus at lower frequencies.

The Pentium processor contains an on-chip
Advanced Programmable Interrupt Controller (APIC).
This APIC implementation supports multiprocessor
interrupt management (with symmetric interrupt
distribution across all processors), multiple I/O
subsystem support, 8259A compatibility, and inter-
processor interrupt support.

The architectural features introduced in this chapter
are more fully described in the 

Pentium

®

 Processor

Family Developer’s Manual

 (Order Number 241428).

The Pentium processor with MMX technology is a
significant addition to the Pentium processor family.
Available at 166, 200 and 233 MHz, it is the first
microprocessor to support Intel’s MMX technology.

The Pentium processor with MMX technology is both
software and pin compatible with previous members
of the Pentium processor family. It contains 4.5
million transistors and is manufactured on lntel's
enhanced 0.35 micron CMOS process which allows
voltage reduction technology for low power and high
density. This enables the Pentium processor with
MMX technology to remain within the thermal

envelope of the original Pentium processor while
providing a significant performance increase.

In addition to the architecture described in the
previous section for the Pentium processor family,
the Pentium processor with MMX technology has
several additional micro-architectural enhancements,
compared to the Pentium processor
133/150/166/200, which are described below:

MMX technology is based on the Single Instruction
Multiple Data (SIMD) technique which enables
increased performance on a wide variety of
multimedia and communications applications. Fifty-
seven new instructions and four new 64-bit data
types are supported in the Pentium processor with
MMX technology. All existing operating system and
application software are fully-compatible with the
Pentium processor with MMX technology.

On-chip level-1 data and code cache sizes have
been doubled to 16 KB each and are 4-way set
associative on the Pentium processor with MMX
technology. Larger separate internal caches improve
performance by reducing average memory access
time and providing fast access to recently-used
instructions and data. The instruction and data
caches can be accessed simultaneously while the
data cache supports two data references
simultaneously. The data cache supports a write-
back (or alternatively, write-through, on a line by line
basis) policy for memory updates.

Dynamic branch prediction uses the Branch Target
Buffer (BTB) to boost performance by predicting the
most likely set of instructions to be executed. The
BTB has been improved on the Pentium processor
with MMX technology to increase its accuracy.
Further, the Pentium processor with MMX technology
has four prefetch buffers that can hold up to four
successive code streams.

An additional pipeline stage has been added and the
pipeline has been enhanced to improve performance.