Intel 200 MHz FV8050366200 User Manual

Product codes
FV8050366200
Page of 51
E
PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
9
5/23/97 10:47 AM    24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
2.0.
PINOUT
2.1.
Pinout and Pin Descriptions
2.1.1.
PENTIUM
®
 PROCESSOR WITH MMX™ TECHNOLOGY PINOUT
INC
INC
INC
FLUSH#
VCC2
VCC3
A10
A6
NC
ADSC#
EADS#
W/R#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A8
A4
A30
VCC2
DET#
PWT
HITM#
BUSCHK#
BE0#
BE2#
BE4#
BE6#
SCYC
A20
A18
A16
A14
A12
A11
A7
A3
AP
D/C#
HIT#
A20M#
BE1#
BE3#
BE5#
BE7#
CLK
RESET
A19
A17
A15
A13
A9
A5
A29
A28
A25
A31
A26
A22
VCC3
A24
A27
A21
VSS
D/P#
A23
INTR
VSS
R/S#
NMI
SMI#
VSS
INIT
IGNNE#
PEN#
VSS
FRCMC#
1
VSS
STPCLK#
VSS
VSS
NC
VSS
TRST#
TMS
VSS
TDO
TDI
TCK
VSS
PICD1
D0
VSS
PICD0
D2
PICCLK
VSS
D3
D1
D5
D4
D7
D6
DP0
D8
D12
DP1
D9
D10
D14
D17
D21
D11
D13
D16
D20
NC
D15
D18
D22
VCC3
BREQ
HLDA
ADS#
VSS
LOCK#
VCC2
SMIACT#
PCD
VSS
PCHK#
PBREQ#
APCHK#
VSS
PBGNT#
PHITM#
PRDY
VSS
HOLD
PHIT#
WB/WT#
VSS
BOFF#
BRDYC#
NA#
VSS
BRDY#
EWBE#
KEN#
VSS
AHOLD
CACHE#
INV
VSS
MI/O#
BP2
BP3
VSS
PM1BP1
PM0BP0
FERR#
VSS
IERR#
D63
DP7
VSS
D62
D61
D60
VSS
D59
D57
D58
VSS
D56
D55
D53
DP6
D51
DP5
D54
D52
D49
D46
D42
D50
D48
D44
D40
D39
INC
D47
D45
DP4
D38
D36
INC
D43
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D37
D35
D33
DP3
D30
D34
D32
D31
D29
D27
INC
D41
VCC2
D28
D25
D26
DP2
D23
D24
D19
VCC3
VCC3
NC
NC
VCC3
VSS
NC
NC
BF1
BF0
VSS
VSS
VSS
NC
CPUTYP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
 
Top Side View
VCC3
VCC3
VCC3
VCC3
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3 VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
NOTE:
1.
The FRCMC# pin is not defined for Pentium
®
 processor with MMX™ technology. Pin Y35 should be left as a "NC" or tied
to V
CC3
 via an external pull-up resistor.
PP0008a
Figure 2.  Pentium
®
 Processor with MMX™ Technology SPGA and PPGA Package Pinout
(Top Side View)