Intel III Xeon 733 MHz 80526KZ733256 User Manual
Product codes
80526KZ733256
TERMINOLOGY
7
2. TERMINOLOGY
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active
state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been
requested. When NMI is high, a non-maskable interrupt has occurred. In the case of lines where the name does not imply
an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is
inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H= High logic
level, L= Low logic level).
The term ‘system bus’ refers to the interface between the processor, system core logic and other bus agents. The system
bus is a multiprocessing interface to processors, memory and I/O. Cache coherency is maintained with other agents on
the system bus through the MESI cache protocol as supported by the HIT# and HITM# bus signals. The term “processor”
refers to the cartridge package that interfaces to a host system board through the SC330.1 interface specification. The
Pentium® III Xeon™ processor at 700 MHz and 900 MHz includes one processor core with integrated L2 cache, an On-
Cartridge Voltage Regulator (OCVR), system bus termination and various system management features. In addition, the
processor includes a thermal plate for cooling solution attachment and a protective cover.
state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been
requested. When NMI is high, a non-maskable interrupt has occurred. In the case of lines where the name does not imply
an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is
inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H= High logic
level, L= Low logic level).
The term ‘system bus’ refers to the interface between the processor, system core logic and other bus agents. The system
bus is a multiprocessing interface to processors, memory and I/O. Cache coherency is maintained with other agents on
the system bus through the MESI cache protocol as supported by the HIT# and HITM# bus signals. The term “processor”
refers to the cartridge package that interfaces to a host system board through the SC330.1 interface specification. The
Pentium® III Xeon™ processor at 700 MHz and 900 MHz includes one processor core with integrated L2 cache, an On-
Cartridge Voltage Regulator (OCVR), system bus termination and various system management features. In addition, the
processor includes a thermal plate for cooling solution attachment and a protective cover.
2.1 S.E.C. CARTRIDGE TERMINOLOGY
The following terms are used in this document and are defined here for clarification:
The following terms are used in this document and are defined here for clarification:
•
Cover — The processor casing on the opposite side of the thermal plate.
•
Core pin — The most external feature of the core package contained within the S.E.C. cartridge used to connect the
core to an internal cartridge substrate trace. For measurement and specification purposes, the cartridge vias used to
connect the core package to the cartridge substrate traces may be considered the core pins.
core to an internal cartridge substrate trace. For measurement and specification purposes, the cartridge vias used to
connect the core package to the cartridge substrate traces may be considered the core pins.
•
Core pad — A feature of a processor die contained within the core package used to connect the die to the core
package. A core pad is defined in the processor signal integrity models and is only observable in simulation.
package. A core pad is defined in the processor signal integrity models and is only observable in simulation.
•
Pentium® III Xeon™ processor at 700 MHz and 900 MHz — The SC330 processor including internal components,
substrate, thermal plate and cover, with either 1MB or 2MB of on-die L2 cache, a 100 MHz system bus, and support
for up to 4-way configurations.
substrate, thermal plate and cover, with either 1MB or 2MB of on-die L2 cache, a 100 MHz system bus, and support
for up to 4-way configurations.
•
FMB (Flexible Motherboard Specification) — A set of specifications to which a design is targeted to allow forward
compatibility with existing and future processors.
compatibility with existing and future processors.
•
L1 cache — Integrated static RAM used to maintain recently used information. Due to code locality, maintaining
recently used information can significantly improve system performance in many applications. The L1 cache is
integrated directly on the processor core.
recently used information can significantly improve system performance in many applications. The L1 cache is
integrated directly on the processor core.
•
L2 cache — The L2 cache is integrated directly on the processor core.
•
OCVR — On Cartridge Voltage Regulator, a new feature that provides the necessary regulated power to the
processor core and Integrated L2 cache and is located on the Pentium® III Xeon™ processor at 700 MHz and 900
MHz substrate.
processor core and Integrated L2 cache and is located on the Pentium® III Xeon™ processor at 700 MHz and 900
MHz substrate.
•
2.8V version — refers to a Pentium® III Xeon™ processor at 700 MHz and 900 MHz that can be powered with +2.8
volts applied to its VCC_CORE pins.
volts applied to its VCC_CORE pins.
•
5V/12V version — refers to a Pentium® III Xeon™ processor at 700 MHz and 900 MHz that can be powered with
either +5.0 or +12.0 volts applied to its VCC_CORE pins.
either +5.0 or +12.0 volts applied to its VCC_CORE pins.
•
HV_EN# — pin added to the SC330.1 definition as a way of differentiating a 5V/12V version Pentium® III Xeon™
processor at 700 MHz and 900 MHz from a 2.8V version. HV_EN# is tied to V
processor at 700 MHz and 900 MHz from a 2.8V version. HV_EN# is tied to V
ss
(ground) on the 5V/12V version, and
is high impedance (floating) on the 2.8V version. This is a reserved (no connect) pin on Pentium® III Xeon™
processors.
processors.
•
Processor substrate — The structure on which components are mounted inside the S.E.C. cartridge (with or
without components attached).
without components attached).
•
Processor core — The processor’s execution engine.
•
S.E.C. cartridge — The processor packaging technology used for the Pentium® II Xeon™ processor family. S.E.C.
is short for "Single Edge Contact” cartridge.
is short for "Single Edge Contact” cartridge.
•
Streaming SIMD Extensions
—
A new set of instructions supported by Intel® processors beginning with the
Pentium® III Xeon™ processor. Single Instruction Multiple Data (SIMD) extensions significantly accelerate
performance of 3D graphics. Besides 3D graphics improvements, the extensions also include additional integer and
cacheability instructions that improve other aspects of performance.
performance of 3D graphics. Besides 3D graphics improvements, the extensions also include additional integer and
cacheability instructions that improve other aspects of performance.
•
Thermal plate — The surface used to connect a heatsink or other thermal solution to the processor.