Intel G870 CM8062307260115 User Manual

Datasheet, Volume 1

25

PCI Express uses packets to communicate information between components. Packets 
are formed in the Transaction and Data Link Layers to carry the information from the 
transmitting component to the receiving component. As the transmitted packets flow 
through the other layers, they are extended with additional information necessary to 
handle packets at those layers. At the receiving side the reverse process occurs and 
packets get transformed from their Physical Layer representation to the Data Link 
Layer representation and finally (for Transaction Layer Packets) to the form that can be 
processed by the Transaction Layer of the receiving device.

The upper layer of the PCI Express architecture is the Transaction Layer. The 
Transaction Layer's primary responsibility is the assembly and disassembly of 
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as 
read and write, as well as certain types of events. The Transaction Layer also manages 
flow control of TLPs.

The middle layer in the PCI Express stack, the Data Link Layer, serves as an 
intermediate stage between the Transaction Layer and the Physical Layer. 
Responsibilities of the Data Link Layer include link management, error detection, and 
error correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the 
Transaction Layer, calculates and applies data protection code and TLP sequence 
number, and submits them to the Physical Layer for transmission across the Link. The 
receiving Data Link Layer is responsible for checking the integrity of received TLPs and 
for submitting them to the Transaction Layer for further processing. On detection of TLP 
error(s), this layer is responsible for requesting retransmission of TLPs until information 
is correctly received, or the Link is determined to have failed. The Data Link Layer also 
generates and consumes packets that are used for Link management functions.

The Physical Layer includes all circuitry for interface operation, including driver and 
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance 
matching circuitry. It also includes logical functions related to interface initialization and 
maintenance. The Physical Layer exchanges data with the Data Link Layer in an 
implementation-specific format, and is responsible for converting this to an appropriate 
serialized format and transmitting it across the PCI Express Link at a frequency and 
width compatible with the remote device.