Intel G870 CM8062307260115 User Manual

Datasheet, Volume 1

27

DMI connects the processor and the PCH chip-to-chip. The DMI is similar to a four-lane 
PCI Express supporting up to 1 GB/s of bandwidth in each direction. 

Only DMI x4 configuration is supported.

DMI can only generate SERR in response to errors—never SCI, SMI, MSI, PCI INT, or 
GPE. Any DMI related SERR activity is associated with Device 0.

The processor is compatible with the PCH and is not compatible with any previous 
(G)MCH or ICH products.

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to 
data link down, after the link was up, then the DMI link hangs the system by not 
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.

Downstream transactions that had been successfully transmitted across the link prior 
to the link going down may be processed as normal. No completions from downstream, 
non-posted transactions are returned upstream over the DMI link after a link down 
event.

This section details the processor integrated graphics 2D, 3D, and video pipeline and 
their respective capabilities.

The integrated graphics is powered by a next generation graphics core and supports 
twelve, fully-programmable execution cores. Full-precision, floating-point operations 
are supported to enhance the visual experience of compute-intensive applications.

The integrated graphics contains several types of components; the graphics engines, 
planes, pipes, port and the Intel FDI. The integrated graphics has a 3D/2D Instruction 
Processing unit to control the 3D and 2D engines respectively. The integrated graphics 
3D and 2D engines are fed with data through the IMC. The outputs of the graphics 
engine are surfaces sent to memory, which are then retrieved and processed by the 
planes. The surfaces are then blended in the pipes and the display timings are 
transitioned from display core clock to the pixel (dot) clock.