Intel G870 BX80623G870 User Manual

64

Datasheet, Volume 1

1.

PCIe bifurcation support varies with the processor and PCH SKUs used.

CFG[17:0]

Configuration Signals: The CFG signals have a default value of '1' if not 

terminated on the board. 

• CFG[1:0]: Reserved configuration lane. A test point may be placed on 

the board for this lane.

• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal

— 1 = Normal operation
— 0 = Lane numbers reversed

• CFG[3]: Reserved
• CFG[4]: Reserved configuration lane. A test point may be placed on 

the board for this lane.

• CFG[6:5]: PCI Express Bifurcation

Note1

— 00 = 1 x8, 2 x4 PCI Express
— 01 = Reserved
— 10 = 2 x8 PCI Express
— 11 = 1 x16 PCI Express

• CFG[17:7]: Reserved configuration lanes. A test point may be placed 

on the board for these lands.

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CMOS

FC_x

FC signals are signals that are available for compatibility with other 

processors. A test point may be placed on the board for these lands. 

PM_SYNC

Power Management Sync: A sideband signal to communicate power 

management status from the platform to the processor.

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CMOS

RESET#

Platform Reset pin driven by the PCH

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CMOS

RSVD

RSVD_NCTF

RESERVED: All signals that are RSVD and RSVD_NCTF must be left 

unconnected on the board. 

No Connect

Non-Critical 

to Function

SM_DRAMRST#

DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One 

common to all channels.

O

CMOS