Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
103
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.14 MH_EXT_STAT
Capture externally asserted MEM_HOT[1:0]# assertion detection.
13.2.1.15 SMB_STAT_[0:1]
SMBus Status
This register provides the interface to the SMBus / I2C SCL and SDA signals that is 
used to access the Serial Presence Detect EEPROM (SPD) or Thermal Sensor on DIMM 
(TSOD) that defines the technology, configuration, and speed of the DIMMs controlled 
by iMC. 
11:8
RW
0x0
MH0_DIMM_ID (mh0_dimm_id):
Hottest DIMM ID for MEM_HOT[0]#. PCU microcode search the hottest 
DIMM temperature and write the hottest temperature and the 
corresponding Hottest DIMM CID/ID.
000 - DIMM0
001 - DIMM1
010 - DIMM2
011- 111 Reserved.
7:0
RW
0x0
MH0_TEMP (mh0_temp):
Hottest DIMM Sensor Reading for MEM_HOT[0]# - This reading represents 
the temperature of the hottest DIMM. PCU microcode search the hottest 
DIMM temperature and write the hottest temperature and the 
corresponding Hottest DIMM CID/ID. Note: iMC hardware load this value 
into the MEMHOT duty cycle generator counter since PCU microcode may 
update this field at different rate/time. This field is ranged from 0 to 127, 
i.e. the most significant bit is always zero.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x120
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x124
Bit
Attr
Default
Description
31:2
RV
-
Reserved.
1:1
RW1C
0x0
MH_EXT_STAT_1 (mh_ext_stat_1):
MEM_HOT[1]# assertion status at this sense period.
Set if MEM_HOT[1]# is asserted externally for this sense period, this running 
status bit will automatically updated with the next sensed value in the next 
MEM_HOT input sense phase.
0:0
RW1C
0x0
MH_EXT_STAT_0 (mh_ext_stat_0):
MEM_HOT[0]# assertion status at this sense period.
Set if MEM_HOT[0]# is asserted externally for this sense period, this running 
status bit will automatically updated with the next sensed value in the next 
MEM_HOT input sense phase.
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