Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
209
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.24 INTL
Interrupt Line Register.
14.2.25 INTPIN
Interrupt Pin Register.
14.2.26 BCTRL
Bridge Control Register.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x3c
Bit
Attr
Default
Description
7:0
RW
RO (Device 0 
Function 0)
0x0
interrupt_line:
N/A for these devices
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x3d
Bit
Attr
Default
Description
7:0
RW_O
0x1
intp:
N/A since these devices do not generate any interrupt on their own
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x3e
Bit
Attr
Default
Description
15:7
RV
-
Reserved. 
6:6
RW
0x0
sbr:
1: Setting this bit triggers a hot reset on the link for the corresponding PCI 
Express port and the PCI Express hierarchy domain subordinate to the port. 
This sends the LTSSM into the Training (or Link) Control Reset state, which 
necessarily implies a reset to the downstream device and all subordinate 
devices. The transaction layer corresponding to port will be emptied by virtue 
of the link going down when this bit is set. This means that in the outbound 
direction, all posted transactions are dropped and nonposted transactions are 
sent a UR response. In the inbound direction, completions for inbound NP 
requests are dropped when they arrive. Inbound posted writes are retired 
normally.Note also that a secondary bus reset will not reset the virtual PCI-
to-PCI bridge configuration registers of the targeted PCI Express port.
0: No reset happens on the PCI Express port.
5:5
RV
-
Reserved. 
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