Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
212
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.30 SDID
Subsystem Identity.
14.2.31 DMIRCBAR
DMI Root Complex Register Block Base Address.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x2e
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x46
Bit
Attr
Default
Description
15:0
RW_O
0x0
subsystem_device_id:
Assigned by the subsystem vendor to uniquely identify the subsystem. The 
default value specifies Intel but can be set to any value once after reset.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Offset:
0x50
Bit
Attr
Default
Description
31:12
RW_LB
0x0
dmircbar:
This field corresponds to bits 32 to 12 of the base address DMI Root 
Complex register space. BIOS will program this register resulting in a base 
address for a 4KB block of contiguous memory address space. This register 
ensures that a naturally aligned 4KB space is allocated within the first 64GB 
of addressable memory space. System Software uses this base address to 
program the DMI Root Complex register set.
All the Bits in this register are locked in LT mode.
Note that this register is kept around on Device#0 even if that port is 
operating as PCIe* port, to provide flexibility of using the VCs in PCIe* 
mode as well. Nobody is asking for this capability right now but maintaining 
that flexibility.
11:1
RV
-
Reserved. 
0:0
RW_LB
0x0
dmircbaren:
0: DMIRCBAR is disabled and does not claim any memory
1: DMIRCBAR memory mapped accesses are claimed and decoded
Notes:
Accesses to registers pointed to by the DMIRCBAR, via message channel or 
JTAG mini-port are not gated by this enable bit that is, accesses these 
registers are honored regardless of the setting of this bit.
BIOS sets this bit only when it wishes to update the registers in the 
DMIRCBAR. It must clear this bit when it has finished changing values. This 
is required to ensure that the registers cannot be changed during an LT 
lock. This bit is protected by LT mode, but the registers in DMIRCBAR are 
not protected except by this bit.
downloadlike
ArtboardArtboardArtboard
Report Bug