Intel E7-8891 v2 CM8063601377422 User Manual

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Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
The Processor Architecture Overview
Uncore Features
This section describes key features supported by each of the uncore modules designed 
specifically for the server and workstation market space. Further details of the key 
modules is provided in subsequent chapters. 
The Ring
The processor implements a proprietary, ring topology, interconnect between the core 
and uncore elements as used by the Intel QPI interface. The processor ring provides a 
high-bandwidth interconnect between the cores and uncore modules. 
Last Level Cache (LLC)
The processor last level cache comprises a 2.5 MB section for each core slice 
instantiated but together they represent one logical cache. 
The LLC tracks the MESIF (Modified, Exclusive, Shared, Invalid, and Forwarded)
for maintaining cache coherency between cores and sockets. For any given cache line, 
the LLC implements core valid bits to track which local core(s) have cached the line in 
their MLC. Core valid bits are also used by LLC to determine which local core(s) are 
needed to be snooped during responding to snoop request. The replacement policy is 
pseudo-least recently used (LRU) with the Invalid way being replaced first. The LLC is a 
20 way cache with the ability to allocate any number of ways. 
Caching Agent (Cbo)
Similar to the last level cache, the caching agent for the processor socket is address-
hashed across Cbo slices. When system BIOS/Firmware disables cores the active Cbo’s 
are not impacted.
The Cbo provides several functions for agent requests:
• Request/snoop proxy: Core/PCIe requests are address hashed to select a Cbo to 
translate and place the request onto the Intel QPI domain. If the last level cache 
slice attached to that Cbo indicates that a core within the socket owns the line (for 
a coherent read), the request is snooped to that local core. 
• Source Address Decoding: The system address decoder is used to determine the 
destination node id for a given request. The source address decoder is replicated in 
all Cbo’s.
• Local Conflict Manager: The Cbo is responsible for ensuring that only one 
coherent request is issued to the system for a specific cache-line in one socket. 
This manages conflicts between all the cores local to the socket.
QuickPath Interconnect (Intel
The Intel QPI module includes two sub-modules: Intel QPI Agent and the ring stop 
which is referred to as R3QPI.
The processor is implemented based on Intel QPI v1.1 spec. The physical/link layers 
are implemented in the Intel QPI Agent sub-module, which provides primary interface 
between the Intel QPI agents on the platform, that is, processors and node controllers. 
This is an Intel proprietary interface for coherent and non-coherent traffic. 
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